CY7C1071DV33

CY7C1071DV33 32-Mbit (2 M × 16) Static RAM 32-Mbit (2 M × 16) Static RAM Features ■ High speed ❐ tAA = 12 ns ■ Low active power ❐ ICC = 250 mA at 83.3 MHz ■ Low Complementary Metal Oxide Semiconductor (CMOS) standby power ❐ ISB2 = 50 mA ■ Operating voltages of 3.3 ± 0.3 V ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Available in Pb-free 48-ball FBGA package Logic Block Diagram Functional Description The CY7C1071DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 16 bits. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: ■ Deselected (CE HIGH) ■ Outputs are disabled (OE HIGH) ■ Both byte high enable and byte low enable are disabled (BHE, BLE HIGH) ■ The write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data ...