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CY7C1059DV33 Dataheets PDF



Part Number CY7C1059DV33
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 8-Mbit (1M x 8) Static RAM
Datasheet CY7C1059DV33 DatasheetCY7C1059DV33 Datasheet (PDF)

Features ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 110 mA at f = 100 MHz ■ Low CMOS standby power ❐ ISB2 = 20 mA ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 44-pin TSOP-II package ■ Offered in standard and high reliability (Q) grades Logic Block Diagram CY7C1059DV33 8-Mbit (1M × 8) Static RAM Functional Description The CY7C1059DV33 is a high performance CMOS S.

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Features ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 110 mA at f = 100 MHz ■ Low CMOS standby power ❐ ISB2 = 20 mA ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 44-pin TSOP-II package ■ Offered in standard and high reliability (Q) grades Logic Block Diagram CY7C1059DV33 8-Mbit (1M × 8) Static RAM Functional Description The CY7C1059DV33 is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input or output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW). The CY7C1059DV33 is available in 44-pin TSOP-II package with center power and ground (revolutionary) pinout. ROW DECODER SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE WE OE INPUT BUFFER 1M x 8 ARRAY COLUMN DECODER POWER DOWN IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 A11 A12 A13 A14 A15 A16 A17 A18 A19 Cypress Semiconductor Corporation • 198 Champion Court Document #: 001-00061 Rev. *H • San Jose, CA 95134-1709 • 408-943-2600 Revised September 12, 2011 Pin Configuration Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current Figure 1. 44-Pin TSOP II Top View NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 NC 43 NC 42 NC 41 A18 40 A17 39 A16 38 A15 37 OE 36 I/O7 35 I/O6 34 VSS 33 VCC 32 I/O5 31 I/O4 30 A14 29 A13 28 A12 27 A11 26 A10 25 A19 24 NC 23 NC –10 10 110 20 CY7C1059DV33 –12 Unit 12 ns 100 mA 20 mA Document #: 001-00061 Rev. *H Page 2 of 11 CY7C1059DV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C Supply voltage on VCC to relative GND[1]....–0.5 V to + 4.6 V DC voltage applied to outputs in high-Z state[1]................................... –0.3 V to VCC + 0.3 V DC input voltage[1]............................... –0.3 V to VCC + 0.3 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage............. ...............................>2001 V (MIL-STD-883, Method 3015) Latch-up current ...................................................... >200 mA Operating Range Range Industrial Ambient Temperature –40 °C to +85 °C VCC 3.3 V ± 0.3 V Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH voltage VOL Output LOW voltage VIH Input HIGH voltage VIL Input LOW voltage[1] IIX Input leakage current IOZ Output leakage current ICC VCC operating supply current ISB1 Automatic CE power-down current — TTL inputs ISB2 Automatic CE power-down current — CMOS inputs Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min IOL = 8.0 mA GND < VIN < VCC GND < VOUT < VCC, output disabled VCC = Max., f = fMAX = 1/tRC –10 Min Max –12 Min Max Unit 2.4 – 2.4 – V – 0.4 – 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 V –0.3 0.8 –0.3 0.8 V –1 +1 –1 +1 μA –1 +1 –1 +1 μA – 110 – 100 mA Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 40 – 35 mA Max. VCC, CE > VCC – 0.3 V, – 20 – 20 mA VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN COUT Input capacitance I/O capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description θJA Thermal resistance (Junction to ambient) θJC Thermal resistance (Junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Max 12 12 TSOP II 51.43 15.8 Unit pF pF Unit °C/W °C/W Notes 1. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-00061 Rev. *H Page 3 of 11 CY7C1059DV33 AC Test Loads and Waveforms AC characteristics (except High-Z) are tested using the load conditions shown in.


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