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TC74AC00FN

Toshiba Semiconductor

QUAD 2 - INPUT NAND GATE

TC74AC00P/F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC00P,TC74AC00F,TC74AC00FN,TC74AC00FT ...


Toshiba Semiconductor

TC74AC00FN

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Description
TC74AC00P/F/FN/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC00P,TC74AC00F,TC74AC00FN,TC74AC00FT Quad 2-Input NAND Gate The TC74AC00 is an advanced high speed CMOS 2-INPUT NAND GATE fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is composed of 3 stages including buffer output, which provide high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: tpd = 3.8 ns (typ.) at VCC = 5 V Low power dissipation: ICC = 4 µA (max) at Ta = 25°C High noise immunity: VNIH = VNIL = 28% VCC (min) Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines. Balanced propagation delays: tpLH ∼− tpHL Wide operating voltage range: VCC (opr) = 2 V to 5.5 V Pin and function compatible with 74F00 Note: xxxFN (JEDEC SOP) is not available in Japan. TC74AC00P TC74AC00F TC74AC00FN TC74AC00FT Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) SOP14-P-300-1.27 : 0.18 g (typ.) SOL14-P-150-1.27 : 0.12 g (typ.) TSSOP14-P-0044-0.65A : 0.06 g (typ.) 1 2006-06-01 Pin Assignment TC74AC00P/F/FN/FT IEC Logic Symbol 1A 1 1B 2 1Y 3 2A 4 2B 5 2Y 6 GND 7 (top view) Truth Table ABY L LH L HH HLH HHL 14 VCC 13 4B 12 4...




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