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74HC05 Dataheets PDF



Part Number 74HC05
Manufacturers NXP
Logo NXP
Description Hex inverter
Datasheet 74HC05 Datasheet74HC05 Datasheet (PDF)

74HC05 Hex inverter with open-drain outputs Rev. 02 — 18 June 2009 Product data sheet 1. General description The 74HC05 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A. The 74HC05 contains six inverters.The outputs of the 74HC05 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly. 2. Features I Wide operating volt.

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74HC05 Hex inverter with open-drain outputs Rev. 02 — 18 June 2009 Product data sheet 1. General description The 74HC05 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A. The 74HC05 contains six inverters.The outputs of the 74HC05 are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up resistors to perform correctly. 2. Features I Wide operating voltage 2.0 V to 6.0 V I Input levels: N For 74HC05: CMOS level I Latch-up performance exceeds 100 mA per JESD 78 Class II level A I ESD protection: N HBM JESD22-A114E exceeds 2000 V N CDM JESD22-C101C exceeds 1000 V I Multiple package options I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC05D −40 °C to +125 °C SO14 74HC05PW −40 °C to +125 °C TSSOP14 74HC05BQ −40 °C to +125 °C DHVQFN14 Description Version plastic small outline package; 14 leads; body width SOT108-1 3.9 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm NXP Semiconductors 4. Functional diagram 74HC05 Hex inverter with open-drain outputs 1 1A 1Y 2 3 2A 2Y 4 5 3A 3Y 6 9 4A 4Y 8 11 5A 5Y 10 13 6A 6Y 12 Fig 1. Logic symbol mna525 5. Pinning information 5.1 Pinning VCC Y A GND 001aaj979 Fig 2. Logic diagram (one gate) 1A 1 1Y 2 2A 3 2Y 4 3A 5 3Y 6 GND 7 Fig 3. Pin configuration SOT108-1 (SO14) 74HC05 14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y 001aaj980 74HC05_2 Product data sheet Rev. 02 — 18 June 2009 © NXP B.V. 2009. All rights reserved. 2 of 13 NXP Semiconductors 74HC05 Hex inverter with open-drain outputs 1A 1 1Y 2 2A 3 2Y 4 3A 5 3Y 6 GND 7 74HC05 14 VCC 13 6A 12 6Y 11 5A 10 5Y 9 4A 8 4Y 001aak276 Fig 4. Pin configuration SOT402-1 (TSSOP14) terminal 1 index area 1Y 2 2A 3 2Y 4 3A 5 3Y 6 74HC05 1 1A 14 VCC GND(1) 13 6A 12 6Y 11 5A 10 5Y 9 4A GND 7 4Y 8 001aak277 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SOT762-1 (DHVQFN14) 5.2 Pin description Table 2. Symbol 1A to 6A 1Y to 6Y GND VCC Pin description Pin 1, 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 6. Functional description Description data input data output ground (0 V) supply voltage Table 3. Input nA L H Function table[1] Output nY Z L [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input clamping current IOK output clamping current VO output voltage VI < −0.5 V or VI > VCC + 0.5 V VO < −0.5 V or VO > VCC + 0.5 V −0.5 [1] [1] [1] −0.5 +7 V 20 mA 20 mA VCC + 0.5 V V 74HC05_2 Product data sheet Rev. 02 — 18 June 2009 © NXP B.V. 2009. All rights reserved. 3 of 13 NXP Semiconductors 74HC05 Hex inverter with open-drain outputs Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit IO ICC IGND Tstg Ptot output current supply current ground current storage temperature total power dissipation VO < VCC + 0.5 V −50 −65 [2] - 25 50 +150 500 mA mA mA °C mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 °C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 °C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC VI VO Tamb ∆t/∆V supply voltage input voltage output voltage ambient temperature input transition rise and fall rate 9. Static characteristics Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Typ Max Unit 2.0 5.0 6.0 V 00−40 - VCC VCC +125 V V °C - - 625 ns/V - 1.67 139 ns/V - - 83 ns/V Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VIH HIGH-level VCC = 2.0 V input voltage VCC = 4.5 V 1.5 1.2 3.15 2.4 - 1.5 3.15 - 1.5 3.15 - V V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VIL LOW-level VCC = 2.0 V input voltage VCC = 4.5 V - 0.8 0.5 - 2.1 1.35 - 0.5 1.35 - 0.5 V 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VOL LOW-level VI = VIH or VIL .


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