MCP37D10-200

MCP37210-200 MCP37D10-200 200 Msps, 12-Bit Low-Power Single-Channel ADC Features Sample Rates: 200 Msps Signal-to-Noise Ratio (SNR) with fIN = 15 MHz and -1 dBFS: - 67 dBFS (typical) at 200 Msps Spurious-Free Dynamic Range (SFDR) with fIN = 15 MHz and -1 dBFS: - 96 dBc (typical) at 200 Msps Power Dissipation with LVDS Digital I/O: - 338 mW at 200 Msps Power Dissipation with CMOS Digital I/O: - 306 mW at 200 Msps, output clock = 100 MHz Power Dissipation Excluding Digital I/O: - 257 mW at 200 Msps Power-Saving Modes: - 80 mW during Standby - 33 mW during Shutdown Supply Voltage: - Digital Section: 1.2V, 1.8V - Analog Section: 1.2V, 1.8V Selectable Full-Scale Input Range: up to 1.8 VP-P Analog Input Bandwidth: 650 MHz Output Interface: - Parallel CMOS, DDR LVDS Output Data Format: - Two's complement or offset binary Optional Output Data Randomizer Device Offering(1) Digital Signal Post-Processing (DSPP) Options: - Decimation filters for improved SNR - Offset and Gain adjustment - Noise-Shaping Requantizer (NSR) - Digital Down-Conversion (DDC) with I/Q or fS/8 output (MCP37D10-200) Built-In ADC Linearity Calibration Algorithms: - Harmonic Distortion Correction (HDC) - DAC Noise Cancellation (DNC) - Dynamic Element Matching (DEM) - Flash Error Calibration Serial Peripheral Interface (SPI) Package Options: - VTLA-124 (9 mm x 9 mm x 0.9 mm) - TFBGA-121 (8 mm x 8 mm x 1.08 mm) No external reference decoupling capacitor required for TFBGA Package...