ZL40221

Features Inputs/Outputs ZL40221 Precision 2:6 LVDS Fanout Buffer with Glitchfree Input Reference Switching and On-Chip Input Termination Data Sheet November 2012 Ordering Information ZL40221LDG1 32 Pin QFN Trays ZL40221LDF1 32 Pin QFN Tape and Reel Accepts two differential or single-ended inputs LVPECL, LVDS, CML, HCSL, LVCMOS Glitch-free switching of references Matte Tin Package size: 5 x 5 mm -40oC to +85oC On-chip input termination and biasing for AC coupled inputs Applications Six precision LVDS outputs Operating frequency up to 750 MHz General purpose clock distribution Low jitter clock trees Power Option for 2.5 V or 3.3 V power supply Current consumption of 97 mA On-chip Low Drop Out (LDO) Regulator for superior power supply rejection Logic translation Clock and data signal restoration Redundant clock distribution Wired communications: OTN, SONET/SDH, GE, 10 GE, FC and 10G FC Wireless communications Performance Ultra low additive jitter of 165 fs RMS High performance micro-processor clock distribution ctrl0 vt0 clk0_p clk0_n clk1_p clk1_n ctrl1 vt1 sel Termination and Bias Termination and Bias Control Buffer Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved. out0_p out0_n out1_p out1_n out2_p out2_n out3_p out3_n out4_p out4_n out5_p out5_n ZL40221 Data Sheet Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....