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AS4C4M32S Dataheets PDF



Part Number AS4C4M32S
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 4M x 32 bit Synchronous DRAM
Datasheet AS4C4M32S DatasheetAS4C4M32S Datasheet (PDF)

AS4C4M32S Revision History AS4C4M32S- 90 Ball TFBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Added 166MHz option -6 clock cycle time Typing error page 1 – change to header of Key Specificatons from AS4C8M32S to AS4C4M32S Typing error Frequency in Ordering information 7-BCN reflected as 133MHz – changed to 143MHz Typing error Part no Header on pages 2-45 Corrected from AS4C2M32S to AS4C4M32S Date February 2013 February 2013 May 2014 May 2014 May 2014 Alliance Me.

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AS4C4M32S Revision History AS4C4M32S- 90 Ball TFBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Added 166MHz option -6 clock cycle time Typing error page 1 – change to header of Key Specificatons from AS4C8M32S to AS4C4M32S Typing error Frequency in Ordering information 7-BCN reflected as 133MHz – changed to 143MHz Typing error Part no Header on pages 2-45 Corrected from AS4C2M32S to AS4C4M32S Date February 2013 February 2013 May 2014 May 2014 May 2014 Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. AS4C4M32S Confidential 4M x 32 bit Synchronous DRAM (SDRAM) Advanced (Rev.3.0, May. /2014) Features  Fast access time from clock: 5.4/5.4 ns  Fast clock rate: 166/143 MHz  Fully synchronous operation  Internal pipelined architecture  Four internal banks (1M x 32-bit x 4bank)  Programmable Mode - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: Sequential & Interleaved - Burst-Read-Single-Write  Burst stop function  Individual byte controlled by DQM0-3  Auto Refresh and Self Refresh  Operating temperature range - Commercial (0 ~ 70°C) - Industrial (-40 ~ 85°C)  4096 refresh cycles/64ms  Single 3.3V ±0.3V. power supply  Interface: LVTTL  90-ball 8 x 13 x 1.2mm TFBGA package - Pb and Halogen Free Overview The 128Mb AS4C4M32S SDRAM is a highspeed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The SDRAM provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Table 1. Key Specifications AS4C4M32S tCK3 Clock Cycle time(min.) tAC3 Access time from CLK (max.) tRAS Row Active time(min.) tRC Row Cycle time(min.) -6/7 6/7.5 ns 5.4/5.4 ns 42/42 ns 60/63 ns Table 2.Ordering Information Part Number Frequency Package AS4C4M32S-6BIN 166MHz 90-ball TFBGA AS4C4M32S-7BCN 143MHz 90-ball TFBGA B: indicates 90-ball (8.0 x 13 x 1.4mm) TFBGA package N: indicates Pb and Halogen Free ROHS Temperature Industrial Commercial Temp Range -40 ~ 85°C 0 ~ 70°C Alliance Memory Confidential 1 Rev. 3.0 May. /2014 Figure 1. Ball Assignment (Top View) 123 A DQ26 DQ24 VSS B DQ28 VDDQ VSSQ C VSSQ DQ27 DQ25 D VSSQ DQ29 DQ30 E VDDQ DQ31 NC F VSS DQM3 A3 G A4 A5 A6 H A7 A8 NC J CLK CKE A9 K DQM1 NC NC L VDDQ DQ8 VSS M VSSQ DQ10 DQ9 N VSSQ DQ12 DQ14 P DQ11 VDDQ VSSQ R DQ13 DQ15 VSS … AS4C4M32S 7 VDD 8 DQ23 9 DQ21 VDDQ VSSQ DQ19 DQ22 DQ20 VDDQ DQ17 DQ18 VDDQ NC DQ16 VSSQ A2 DQM2 VDD A10 A0 A1 NC BA1 A11 BA0 CS# RAS# CAS# WE# DQM0 VDD DQ7 VSSQ DQ6 DQ5 VDDQ DQ1 DQ3 VDDQ VDDQ VSSQ DQ4 VDD DQ0 DQ2 Alliance Memory Confidential 2 Rev. 3.0 May. /2014 Figure 2. Block Diagram CLK CKE CS# RAS# CAS# WE# CLOCK BUFFER COMMAND DECODER CONTROL SIGNAL GENERATOR A10/AP A0 A9 A11 BA0 BA1 ~ COLUMN COUNTER ADDRESS BUFFER REFRESH COUNTER MODE REGISTER Row Decoder Row Decoder Row Decoder Row Decoder AS4C4M32S 4096 x 256 x 32 CELL ARRAY (BANK #0) Column Decoder DQ Buffer DQM0~3 ~ DQ0 DQ31 4096 x 256 x 32 CELL ARRAY (BANK #1) Column Decoder 4096 x256 x 32 CELL ARRAY (BANK #2) Column Decoder 4096 x 256 x 32 CELL ARRAY (BANK #3) Column Decoder Alliance Memory Confidential 3 Rev. 3.0 May. /2014 AS4C4M32S Pin Descriptions Table 1. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the .


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