FTD2012

FTD2012 N- Channel Silicon MOS FET Load S/W USE TENTATIVE Features Low ON-state resistance. 4V drive. Mount height of 1.1mm. Complex Type enabling high density mount Absolute Maximum Ratings / Ta=25°C Drain to Source Voltage Gate to Source Voltage Drain Current(DC) Drain Current(Pulse) Allowable power Dissipation Total Dissipation Channel Temperature Storage Temperature Electrical Characteristics / Ta=25°C Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Cutoff Voltage Forward Transfer Admittance Static Drain to Source On State Resistance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-ON Delay Time Rise Time Turn-OFF Delay Time Fall Time Total Gate Charge Gate Source Charge Gate Drain Charge Diode Forward Voltage Marking : D2012 Switching Time Test Circuit VIN 10V 0V VIN PW=10µS D.C.≤1% D VDD=15V D2 ID=4.5A RL=3.3Ω VOUT 6.4 4.5 S2 S2 G2 0.65 8 7 6 5 3.0 0.95 0.425 unit VDSS VGSS ID IDP PD PT Tch Tstg 30 ±20 4.5 20 0.8 1.3 150 --55 to +150 min V(BR)DSS IDSS IGSS VGS(off) | yfs | RDS(on) 1 RDS(on) 2 Ciss Coss Crss td(on) tr td(off) tf Qg Qgs Qgd VSD ID=1mA , VGS=0 VDS=30V , VGS=0 VGS=±16V , VDS=0 VDS=10V , ID=1mA VDS=10V , ID=4.5A ID=4.5A , VGS=10V ID=4A , VGS=4V VDS=10V , f=1MHz VDS=10V , f=1MHz VDS=10V , f=1MHz See Specified Test Circuit " " " VDS=10V, VGS=10V, ID=4.5A IS=4.5A , VGS=0 Case Outline TSSOP8(unit:mm) PW≤10µS, dutycycle≤1% Mounted on ceramic board (1000mm2 ! 0.8mm) 1unit Mounted on c...