Document
Freescale Semiconductor Data Sheet: Technical Data
Document Number: MMA52xxAKW Rev. 0, 09/2012
Xtrinsic MMA52xxAKW PSI5 Inertial Sensor
The MMA52xxAKW family, a SafeAssure solution, includes the PSI5 Version 1.3 asynchronous mode compatible overdamped X-axis satellite accelerometers.
Features
• ±60g to ±480g Full-Scale Range • 400 Hz, 3-Pole Low-Pass Filter • Single Pole, High-Pass Filter with Fast Startup and Output Rate Limiting • PSI5 Version 1.3 Asynchronous Mode Compatible
– PSI5-A10P-228/1L Compatible – Baud Rate: 125 kBaud – 10-bit Data – Even Parity Error Detection • 16 μs Internal Sample Rate, with Interpolation to 1 μs • Pb-Free 16-Pin QFN, 6 by 6 Package • Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C) (http://www.aecouncil.com/)
Typical Applications
• Airbag Front and Side Crash Detection
Device MMA5206AKW MMA5212AKW MMA5224AKW MMA5248AKW MMA5206AKWR2 MMA5212AKWR2 MMA5224AKWR2 MMA5248AKWR2
ORDERING INFORMATION
Axis
Range
Package
X 60g
2086-01
X 120g
2086-01
X 240g
2086-01
X 480g
2086-01
X 60g
2086-01
X 120g
2086-01
X 240g
2086-01
X 480g
2086-01
Shipping Tubes Tubes Tubes Tubes
Tape & Reel Tape & Reel Tape & Reel Tape & Reel
MMA52xxAKW
Bottom View
16-PIN QFN CASE 2086-01
Top View
VSSA NC TEST VBUF
16 15 14 13
VCC VSS IDATA VSS
1 2 3 4
17 56
12 VSSA 11 VREGA 10 CS 9 VREG 78
NC SLCK DOUT
DIN
PIN CONNECTIONS
© 2012 Freescale Semiconductor, Inc. All rights reserved.
Application Diagram
C4 C5 C6
Note: Pin names and references may differ from PSI5 V1.3 pin names and references
VVBVUBFUF
VCC
VREG
IDATA
MMA51xx
VREGA
CS SCLK DO
VSSA VSS
DI
R1 R2
C2 C3
VCE
C1
VSS
Ref Des
C1 C3 C2 C4, C5, C6 R1 R2
Type
Ceramic Ceramic Ceramic Ceramic General Purpose General Purpose
Figure 1. Application Diagram
External Component Recommendations
Description
Purpose
2.2 nF, 10%, 50V minimum, X7R
VCC Power Supply Decoupling and Signal Damping
470 pF, 10%, 50V minimum, X7R
IDATA Filtering and Signal Damping
15 nF, 10%, 50V minimum, X7R 1 μF, 10%, 10V minimum, X7R
VCC Power Supply Decoupling Voltage Regulator Output Capacitor(s)
82Ω, 5%, 200 PPM 27Ω, 5%, 200 PPM
VCC Filtering and Signal Damping IDATA Filtering and Signal Damping
Device Orientation
xxxxxxx xxxxxxx
xxxxxxx xxxxxxx
xxxxxxx xxxxxxx
X: 0g
X: +1g
X: 0g
xxxxxxx xxxxxxx X: -1g
X: 0g
EARTH GROUND
Figure 2. Device Orientation Diagram
X: 0g
MMA52xxAKW 2
Sensors Freescale Semiconductor, Inc.
Internal Block Diagram
VCC
CS SCLK
DIN DOUT
SPI
Buffer Voltage Regulator
VBUF
Reference VREF Voltage
Digital Voltage Regulator
VREG
Analog Voltage Regulator
VREGA VBUF
Low Voltage Detection
Control Logic
OTP Array
Sync Pulse Detection
Programming Interface
Serial Encoder
Self-Test Interface
g-cell
VREG
VREGA
VREG
ΣΔ Converter
Control Status In Out
DSP
SINC Filter
IIR LPF Compensation
Offset Monitor
HPF
Figure 3. Block Diagram
VBUF VREG VREGA VSSA
VCC IDATA
VSS
Sensors Freescale Semiconductor, Inc.
MMA52xxAKW 3
1 Pin Connections
VSSA NC TEST VBUF
16 15 14 13
VCC VSS IDATA VSS
1 2 3 4
17 567
12 VSSA 11 VREGA 10 CS
9 VREG 8
NC SLCK DOUT
DIN
Figure 4. Top View, 16-Pin QFN Package
Table 1. Pin Description
Pin
Pin Name
Formal Name
Definition
1 VCC
Supply
This pin is connected to the PSI5 power and data line through a resistor and supplies power to the device. An external capacitor must be connected between this pin and VSS. Reference Figure 1.
2 VSS Digital GND This pin is the power supply return node for the digital circuitry.
3 IDATA
Response Current
This pin is connected to the PSI5 power and data line through a resistor and modulates the response current for PSI5 communication. Reference Figure 1.
4 VSS Digital GND This pin is the power supply return node for the digital circuitry. 5 NC Not Connected This pin must be left unconnected in the application.
6 SCLK
SPI Clock
This input pin provides the serial clock to the SPI port for test purposes. An internal pulldown device is connected to this pin. This pin must be grounded or left unconnected in the application.
7
DOUT
SPI Data Out
This pin functions as the serial data output from the SPI port for test purposes. This pin must be left unconnected in the application.
8
DIN
SPI Data In
This pin functions as the serial data input to the SPI port for test purposes. An internal pulldown device is connected to this pin. This pin must be grounded or left unconnected in the application.
9 VREG 10 CS
Digital Supply
Chip Select
This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1.
This input pin provides the chip select to the SPI port for test purposes. An internal pullup device is connected to this pin.This pin must be left unconnected in the application.
11 VREGA 12 VSSA
Analog Supply
Analog GND
This pin is connected to the power supply for the internal analog circuitry. An external capac.