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Freescale Semiconductor Technical Data
DSP56321 Rev. 11, 2/2005
DSP56321
24-Bit Digital Signal Processor
3 16 6 6
Memory Expansion Area
SCI
Triple Timer
Address Generation
Unit Six Channel DMA Unit
Bootstrap ROM
Internal Data Bus Switch
Clock Generator
PLL
EXTAL XTAL
RESET PINIT/NMI
PIO_EB PM_EB XM_EB YM_EB
HI08
ESSI
EFCOP
Peripheral Expansion Area
Program RAM
32 K × 24 bits or
31 K × 24 bits
and Instruction
Cache 1024 × 24 bits
X Data
RAM 80 K × 24 bits
Y Data
RAM 80 K × 24 bits
YAB XAB PAB DAB
External Address
Bus Switch
18 Address
24-Bit DSP56300
Core
DDB YDB XDB PDB GDB
External Bus
Interface and
I - Cache Control
10 Control
External Data Bus Switch
24 Data
Program Interrupt Controller
Program Decode Controller
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
Program Address Generator
Power
Management
Data ALU 24 × 24 + 56 →56-bit MAC
Two 56-bit Accumulators
JTAG
56-bit Barrel Shifter
OnCE™
5 DE
Figure 1. DSP56321 Block Diagram
The DSP56321 is intended for applications requiring a large amount of internal memory, such as networking and wireless infrastructure applications. The onboard EFCOP can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolutionbased algorithms.
What’s New?
Rev. 11 includes the following changes: • Adds lead-free packaging and
part numbers.
The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 codecompatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller (see Figure 1).
The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550 MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. This device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
© Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.
Table of Contents
Chapter 1
Chapter 2 Chapter 3 Chapter 4
Data Sheet Conventions .......................................................................................................................................ii Features ...............................................................................................................................................................iii Target Applications ............................................................................................................................................. iv Product Documentation .......................................................................................................................................v
Signals/Connections 1.1 Power ................................................................................................................................................................1-3 1.2 Ground ..............................................................................................................................................................1-3 1.3 Clock.................................................................................................................................................................1-3 1.4 External Memory Expansion Port (Port A) ......................................................................................................1-4 1.5 Interrupt and Mode Control ..............................................................................................................................1-6 1.6 Host Interface (HI08)........................................................................................................................................1-7 1.7 Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-10 1.8 Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-11 1.9 Serial Communication Interface (SCI) ...........................................................................................................1-12 1.10 Timers .............................................................................................................................................................1-13 1.11 JTAG and OnCE Interface ..............................................................................................................................1-14
Specifications 2.1 Maximum Ratings.............................................................................................................................................2-1 2..