Document
ICX075AL
Diagonal 8mm (Type 1/2) Progressive Scan CCD Image Sensor with Square Pixel for CCIR B/W Video Cameras
Description The ICX075AL is an interline CCD solid-state
image sensor suitable for CCIR black-and-white video cameras. Progressive scan allows all pixels signals to be output independently within approximately 1/50 second. This chip features an electronic shutter with variable charge-storage time which makes it possible to realize full-frame still image without mechanical shutter. Individual pixels in a square matrix make this device suitable for image input and processing applications.
High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors.
Features • Progressive scan allows individual readout of the
image signals from all pixels. • High vertical resolution (580TV-lines) still picture
without mechanical shutter. • Square pixel unit cell • High resolution, high sensitivity, low dark current • Continuous variable-speed shutter • Low smear • Excellent antiblooming characteristics • Reset gate: 5V drive (bias: no adjustment)
22 pin DIP (Cer-DIP)
Pin 1
2
V
3 Pin 12
H
8 38
Optical black position (Top View)
Device Structure • Image size: • Number of effective pixels: • Total number of pixels: • Interline CCD image sensor • Chip size: • Unit cell size: • Optical black:
• Number of dummy bits:
• Substrate material:
Diagonal 8mm (Type 1/2)
782 (H) × 582 (V)
approx. 460K pixels
823 (H) × 592 (V)
approx. 490K pixels
8.10mm (H) × 6.33mm (V) 8.3µm (H) × 8.3µm (V) Horizontal (H) direction: Front 3 pixels, rear 38 pixels Vertical (V) direction: Front 8 pixels, rear 2 pixels Horizontal 19 Vertical 5 Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95309G07-PS
VOUT2 CGG2 VOUT1 CGG1 GND VHOLDφ Vφ1 Vφ2 Vφ3 HIS HIGφ1
Block Diagram and Pin Configuration (Top View)
11 10 9 8 7 6 5 4 3 2 1
ICX075AL
Vertical Register
Horizontal Register 1 Horizontal Register 2
Note)
Note)
: Photo sensor
12 13 14 15 16 17 18 19 20 21 22
VDD RG VL SUB Hφ1 Hφ2 HHGφ1 HHGφ2 HIG2 POGφ VOGφ
Pin Description
Pin No. Symbol 1 HIGφ1 2 HIS
Description Test pin ∗2 Test pin ∗2
3 Vφ3
Vertical register transfer clock
4 Vφ2
Vertical register transfer clock
5 Vφ1
Vertical register transfer clock
6
VHOLDφ
Vertical register final stage accumulation clock
7 GND 8 CGG1
GND
Output amplifier 1 gate ∗1 decoupling capacitor
9 VOUT1 10 CGG2
Signal output 1
Output amplifier 2 gate ∗1 decoupling capacitor
11 VOUT2 Signal output 2
Pin No. Symbol
Description
12 VDD
Supply voltage
13 RG
Reset gate clock
14 VL
Protective transistor bias
15 SUB Substrate (overflow drain)
16 Hφ1
Horizontal register transfer clock
17 Hφ2
Horizontal register transfer clock
18 HHGφ1 Inter-horizontal register transfer clock
19 HHGφ2 Inter-horizontal register transfer clock
20 HIG2
Test pin ∗2
21 POGφ Test pin ∗2
22
VOGφ
Vertical register final stage transfer clock
∗1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1µF or more. ∗2 Regarding the test pins: apply the same voltage as the supply voltage to HIS, and ground HIGφ1, HIG2, and
POGφ.
–2–
Absolute Maximum Ratings
Item
Substrate voltage SUB – GND
Supply voltage
VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 – GND VDD, VOUT1, VOUT2, HIS, CGG1, CGG2 – SUB
Clock input voltage
Vφ1, Vφ2, Vφ3, VHOLDφ, VOGφ – GND Vφ1, Vφ2, Vφ3, VHOLDφ, VOGφ – SUB
Voltage difference between vertical clock input pins
Voltage difference between horizontal clock input pins
Hφ1, Hφ2 – VOGφ
Hφ1, Hφ2 – GND
Hφ1, Hφ2 – SUB
VL – SUB
Vφ2, Vφ3, VDD, VOUT1, VOUT2, HIS, HIGφ1, HIG2, POGφ – VL
RG – GND
Vφ1, CGG1, CGG2, Hφ1, Hφ2, HHGφ1, HHGφ2, VOGφ, VHOLDφ – VL
Storage temperature
Operating temperature ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
ICX075AL
Ratings Unit Remarks
–0.3 to +55 V
–0.3 to +18 V
–55 to +10 V
–15 to +20 V
to +10 to +15
V V ∗1
to +17
V
–17 to +17 V
–10 to +15 V
–55 to +10 V
–65 to +0.3 V
–0.3 to +27.5 V
–0.3 to +22.5 V
–0.3 to +17.5 V
–30 to +80 °C
–10 to +60 °C
–3–
ICX075AL
Bias Conditions
Item Supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
Protective transistor bias
Symbol VDD
Min. 14.55
VSUB
9.0
Indicated voltage – 0.1
VL
Typ. 15.0
Indicated voltage
∗2
Max. 15.45
18.5
Unit Remarks V V ∗1
Indicated voltage + 0.1
V
DC Characteristics
Item Symbol Min. Typ. Max. Unit Remarks
Supply current Input current Input current
IDD IIN1 IIN2
10 mA 1 µA 10 µA
∗3 ∗4
∗1 Indications of substrate voltage (VSUB) setting value The setting v.