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NAND512W4A2D Dataheets PDF



Part Number NAND512W4A2D
Manufacturers Numonyx
Logo Numonyx
Description SLC NAND flash memories
Datasheet NAND512W4A2D DatasheetNAND512W4A2D Datasheet (PDF)

NAND512xxA2D 512-Mbit, 528-byte/264-word page, 1.8 V/3 V, SLC NAND flash memories Features „ High density SLC NAND flash memories – 512 Mbit memory array – Cost effective solutions for mass storage applications „ NAND interface – x8 or x16 bus width – Multiplexed address/data „ Supply voltage: 1.8 V, 3 V „ Page size – x8 device: (512 + 16 spare) bytes – x16 device: (256 + 8 spare) words „ Block size – x8 device: (16 K + 512 spare) bytes – x16 device: (8 K + 256 spare) words „ Page read/program .

  NAND512W4A2D   NAND512W4A2D


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NAND512xxA2D 512-Mbit, 528-byte/264-word page, 1.8 V/3 V, SLC NAND flash memories Features „ High density SLC NAND flash memories – 512 Mbit memory array – Cost effective solutions for mass storage applications „ NAND interface – x8 or x16 bus width – Multiplexed address/data „ Supply voltage: 1.8 V, 3 V „ Page size – x8 device: (512 + 16 spare) bytes – x16 device: (256 + 8 spare) words „ Block size – x8 device: (16 K + 512 spare) bytes – x16 device: (8 K + 256 spare) words „ Page read/program – Random access: 12 µs (3 V)/15 µs (1.8 V) (max) – Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min) – Page program time: 200 µs (typ) „ Copy back program mode „ Fast block erase: 1.5 ms (typ) „ Status register „ Electronic signature „ Chip Enable ‘don’t care’ „ Hardware data protection: program/erase locked during power transitions „ Security features – OTP area TSOP48 12 x 20 mm (N) FBGA VFBGA63 9 x 11 x 1.05 mm (ZA) – Serial number (unique ID) „ Data integrity – 100,000 program/erase cycles (with ECC) – 10 years data retention „ RoHS compliant packages „ Development tools – Error correction code models – Bad blocks management and wear leveling algorithms – Hardware simulation models Table 1. Device summary NAND512xxA2D NAND512R3A2D NAND512R4A2D NAND512W3A2D NAND512W4A2D July 2010 210217 - Rev 9 1/52 www.numonyx.com 1 Contents Contents NAND512xxA2D 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.9 Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.10 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.1 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.2 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.3 Sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/52 NAND512xxA2D Contents 6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.7 Read status register . . . . . . . . . . . . . . . . . . . . . . ..


NAND512W3A2D NAND512W4A2D IPB100P03P3L-04


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