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GAL20RA10 Dataheets PDF



Part Number GAL20RA10
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description High-Speed Asynchronous E2CMOS PLD Generic Array Logic
Datasheet GAL20RA10 DatasheetGAL20RA10 Datasheet (PDF)

GAL20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic™ Features • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typical Icc • ACTIVE PULL-UPS ON ALL PINS • E CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (.

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GAL20RA10 High-Speed Asynchronous E2CMOS PLD Generic Array Logic™ Features • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typical Icc • ACTIVE PULL-UPS ON ALL PINS • E CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100 ms) — 20 Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — Independent Programmable Clocks — Independent Asynchronous Reset and Preset — Registered or Combinatorial with Polarity — Full Function and Parametric Compatibility with PAL20RA10 • PRELOAD AND POWER-ON RESET OF ALL REGISTERS — 100% Functional Testability • APPLICATIONS INCLUDE: — State Machine Control — Standard Logic Consolidation — Multiple Clock Logic Designs • ELECTRONIC SIGNATURE FOR IDENTIFICATION 2 Functional Block Diagram PL 8 I OLMC I/O/Q 8 I OLMC I/O/Q 8 I OLMC I/O/Q PROGRAMMABLE AND-ARRAY (80X40) 8 OLMC I I/O/Q 8 OLMC I I/O/Q 8 OLMC I I/O/Q 8 OLMC I I/O/Q 8 I OLMC I/O/Q 8 I OLMC I/O/Q 8 I OLMC I/O/Q Description The GAL20RA10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor’s E2CMOS circuitry achieves power levels as low as 75mA typical ICC which represents a substantial savings in power when compared to bipolar counterparts. E2 technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL20RA10 is a direct parametric compatible CMOS replacement for the PAL20RA10 device. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified. OE Pin Configuration DIP PLCC I/O/Q I/O/Q Vcc PL NC PL I I I 25 I/O/Q I/O/Q 1 24 Vcc I/O/Q I/O/Q 4 I I I NC I I I 11 12 9 7 5 2 28 26 I I I I I I I GND GAL 20RA10 6 18 I I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q GAL20RA10 Top View 14 16 23 I/O/Q NC 21 I/O/Q I/O/Q 19 18 I/O/Q GND OE I I I/O/Q I/O/Q NC 12 13 OE Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037.


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