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S5K437CX
(1/4" VGA CMOS Image Sensor) DATA SHEET
Revision 1.1
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DOCUMENT TITLE
1/4" Optical Size 640 × 480 (VGA) 2.8V CMOS Image Sensor
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REVISION HISTORY
Revision No.
History
0.0 Initial Draft
1.0 Changed the operation frequency (30MHz → 24.54MHz).
Added the shutter operation range limit. Added recommended value for selection of OB_AREA. Added CHIP pad description.
1.1 Added AC characteristic timing diagram (include Standby timing diagram)
Draft Date Mar, 01. 2004 May, 18. 2004
July, 15. 2004
Remark
Table of Contents
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Introduction .................................................................................................................................................................2 Features ......................................................................................................................................................................2 Products ......................................................................................................................................................................2 Block Diagram.............................................................................................................................................................3 Pixel Array...................................................................................................................................................................4 Chip Pad Configuration...............................................................................................................................................5 Chip Pad Description ..................................................................................................................................................6 Package Pin Configuration (48 CLCC, Test Only) .....................................................................................................7 Package Pin Description (48CLCC, Test Only) ..........................................................................................................8 Maximum Absolute Limit.............................................................................................................................................9
Electrical Characteristics .......................................................................................................................................10
Control Registers ......................................................................................................................................................13 Operation Description ...............................................................................................................................................18 Timing Chart..............................................................................................................................................................25
Vertical Timing Diagram ........................................................................................................................................25
48CLCC Package Dimension (Test Only) ................................................................................................................29
List of Figures
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Figure Number
Title
Page Number
Figure 1. Block Diagram ............................................................................................................................................. 3
Figure 2. Pixel Array Configuration............................................................................................................................. 4
Figure 3. Pin Configuration......................................................................................................................................... 7
Figure 4. WOI definition ............................................................................................................................................ 18
Figure 5. Bayer Space Sub-Sampling Examples ..................................................................................................... 19
Figure 6. Relative Channel Gain .............................................................................................................................. 20
Figure 7. Relative Global Gain ................................................................................................................................. 21
Figure 8. Recommended Minimum Global Gain Control Value ............................................................................... 21
Figure 9. Quadrisectional Global Gain Control......................................................................................................... 22
Figure 10. I2C Bus Write Cycle ................................................................................................................................. 23
Figure 11. I2C Bus Read Cycle.....