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UPA1816 Dataheets PDF



Part Number UPA1816
Manufacturers NEC
Logo NEC
Description MOS FIELD EFFECT TRANSISTOR
Datasheet UPA1816 DatasheetUPA1816 Datasheet (PDF)

DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1816 P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING DESCRIPTION The µPA1816 is a switching device which can be driven directly by a 1.8 V power source. This device features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power management of notebook computers and so on. FEATURES • 1.8 V drive available • Low on-state resistance RDS(on)1 = 15 mΩ MAX. (VGS = −4.5 V, ID = −4.5 A) RDS(on)2 = .

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DATA SHEET MOS FIELD EFFECT TRANSISTOR µ PA1816 P-CHANNEL MOS FIELD EFFECT TRANSISTOR FOR SWITCHING DESCRIPTION The µPA1816 is a switching device which can be driven directly by a 1.8 V power source. This device features a low on-state resistance and excellent switching characteristics, and is suitable for applications such as power management of notebook computers and so on. FEATURES • 1.8 V drive available • Low on-state resistance RDS(on)1 = 15 mΩ MAX. (VGS = −4.5 V, ID = −4.5 A) RDS(on)2 = 16 mΩ MAX. (VGS = −4.0 V, ID = −4.5 A) RDS(on)3 = 22.5 mΩ MAX. (VGS = −2.5 V, ID = −4.5 A) RDS(on)4 = 41.5 mΩ MAX. (VGS = −1.8 V, ID = −2.5 A) • Built-in G-S protection diode against ESD PACKAGE DRAWING (Unit: mm) 85 1, 2, 3 : Source 4 : Gate 5, 6, 7, 8: Drain 1.2 MAX. 1.0 ±0.05 0.25 14 3° +5° –3° 0.1 ±0.05 0.5 0.6 +0.15 –0.1 3.15 ±0.15 3.0 ±0.1 6.4 ±0.2 4.4 ±0.1 1.0 ±0.2 0.145 ±0.055 ORDERING INFORMATION PART NUMBER µPA1816GR-9JG PACKAGE Power TSSOP8 0.65 0.8 MAX. 0.27 +0.03 –0.08 0.10 M 0.1 ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS Gate to Source Voltage (VDS = 0 V) VGSS Drain Current (DC) (TA = 25°C) Drain Current (pulse) Note1 Total Power Dissipation Note2 ID(DC) ID(pulse) PT Channel Temperature Tch Storage Temperature Tstg −12 m 8.0 m 9.0 m 36 2.0 150 −55 to +150 V V A A W °C °C Notes 1. PW ≤ 10 µs, Duty Cycle ≤ 1% 2. Mounted on ceramic substrate of 5000 mm2 x 1.1 mm EQUIVALENT CIRCUIT Drain Gate Body Diode Gate Protection Diode Source Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G16252EJ1V0DS00 (1st edition) Date Published July 2002 NS CP(K) Printed in Japan © 2002 µ PA1816 ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS Zero Gate Voltage Drain Current Gate Leakage Current Gate Cut-off Voltage Forward Transfer Admittance Drain to Source On-state Resistance Input Capacitance IDSS IGSS VGS(off) | yfs | RDS(on)1 RDS(on)2 RDS(on)3 RDS(on)4 Ciss VDS = −12 V, VGS = 0 V VGS = m 8.0 V, VDS = 0 V VDS = −10 V, ID = −1.0 mA VDS = −10 V, ID = −4.5 A VGS = −4.5 V, ID = −4.5 A VGS = −4.0 V, ID = −4.5 A VGS = −2.5 V, ID = −4.5 A VGS = −1.8 V, ID = −2.5 A VDS = −10 V Output Capacitance Coss VGS = 0 V Reverse Transfer Capacitance Turn-on Delay Time Rise Time Crss f = 1.0 MHz td(on) VDD = −10 V, ID = −4.5 A tr VGS = −4.0 V Turn-off Delay Time td(off) RG = 10 Ω Fall Time Total Gate Charge Gate to Source Charge Gate to Drain Charge tf QG VDD = −10 V QGS VGS = −4.0 V QGD ID = −9.0 A Body Diode Forward Voltage VF(S-D) IF = 9.0 A, VGS = 0 V Reverse Recovery Time trr IF = 9.0 A, VGS = 0 V Reverse Recovery Charge Qrr di/dt = 100 A/ µs MIN. TYP. MAX. UNIT −0.45 −0.75 −1.0 m 10 −1.5 µA µA V 11 22 S 12.0 15 mΩ 12.5 16 mΩ 16.2 22.5 mΩ 23.7 41.5 mΩ 1570 pF 400 pF 240 pF 16 ns 132 ns 223 ns 295 ns 15 nC 3.0 nC 4.5 nC 0.82 V 490 ns 580 nC TEST CIRCUIT 1 SWITCHING TIME D.U.T. RG PG. VGS (−) 0 τ τ = 1µs Duty Cycle ≤ 1% RL VDD VGS (−) VGS Wave Form 10% 0 90% VGS VDS (−) 90% VDS VDS Wave Form 0 td(on) 10% 10% tr td(off) 90% tf ton toff TEST CIRCUIT 2 GATE CHARGE D.U.T. IG = −2 mA PG. 50 Ω RL VDD 2 Data Sheet G16252EJ1V0DS µ PA1816 TYPICAL CHARACTERISTICS (TA = 25°C) DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 120 TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.5 PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 100 80 60 40 20 0 0 25 50 75 100 125 150 175 TA - Ambient Temperature - °C 2 1.5 1 0.5 Mounted on ceramic substrate of 5000 mm2 x 1.1 mm 0 0 25 50 75 100 125 150 175 TA - Ambient Temperature - °C FORWARD BIAS SAFE OPERATING AREA -100 ID(pulse) -10 ID(DC) PW = 1 ms ID - Drain Current - A -1 RDS(on) Limited (VGS = −4.5 V) DC 10 ms 100 ms -0.1 Single Pulse Mounted on ceramic substrate of 5000 mm2 x 1.1 mm -0.01 -0.1 -1 -10 -100 VDS - Drain to Source Voltage - V TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH 100 62.5°C/W rth(ch-A) - Transient Thermal Resistance - °C/W 10 1 1m 10 m Single Pulse Mounted on ceramic substrate of 5000 mm2 x 1.1 mm 100 m 1 10 PW - Pulse Width - s 100 1000 Data Sheet G16252EJ1V0DS 3 ID - Drain Current - A DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE -40 Pulsed −4.0 V -30 VGS = −4.5 V −2.5 V -20 −1.8 V -10 0 0 -0.2 -0.4 -0.6 -0.8 -1 VDS - Drain to Source Voltage - V GATE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE -1 VDS = −10 V ID = −1.0 mA -0.8 -0.6 ID - Drain Cu.


UGN3013U UPA1816 B794


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