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Z8000 Dataheets PDF



Part Number Z8000
Manufacturers Zilog
Logo Zilog
Description Communications Controller
Datasheet Z8000 DatasheetZ8000 Datasheet (PDF)

Zilog Z8030 Z8000® Z-SCC Serial Communications Controller Product Specification Features General Description • Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal OSCillator, baud rate generator, and Digital Phase-Locked Loop for clock recovery. • Multi-protocol operation under program control; programmable for NRZ, NRZI, or FM data encoding. • Asynchronous mode with five to eight bits and one, one and one-half, or two stop bits per character; programmable.

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Zilog Z8030 Z8000® Z-SCC Serial Communications Controller Product Specification Features General Description • Two independent, 0 to 1.5M bit/second, fullduplex channels, each with a separate crystal OSCillator, baud rate generator, and Digital Phase-Locked Loop for clock recovery. • Multi-protocol operation under program control; programmable for NRZ, NRZI, or FM data encoding. • Asynchronous mode with five to eight bits and one, one and one-half, or two stop bits per character; programmable clock factor; break detection and generation; parity, overrun, and framing error detection. • Synchronous mode with internal or external character synchronization on one or two The Z8030 Z-SCC Serial Communications Controller is a dual-channel, multi-protocol data communications peripheral designed for use with the Zilog Z-Bus. The Z-SCC functions as a serial-to-parallel, parallel-to-serial converter/controller. The Z-SCC can be softwareconfigured to satisfy a wide variety of serial April 1985 synchronous characters and CRC generation and checking with CRC-16 or CRC-CCITT preset to either Is or Os. • SDLC/HDLC mode with comprehensive frame-level control, automatic zero insertion and deletion, I-field residue handling, abort generation and detection, CRC generation and checking, and SDLC Loop mode operation. • Local Loopback and Auto Echo modes. • 1.544M bit/second Tl digital trunk compatible version available. communications applications. The device contains a variety of new, sophisticated internal functions including on-chip baud rate generators, Digital Phase-Locked Loops, and crystal oscillators that dramatically reduce the need for external logic. 2016-001,002 ADDRESS' DATA BUS AD, TxDA } SERIAL AD, RIlOA _ _ DATA AD, TRxCA ........-} CHANNEL AD, RTxCA .--- CLOCKS AD, AD, CHANNEL AD, CONTROLS FOR MODEM, ADo DMA,OR As OTHER OS R/W es, } SERIAL _ _ DATA esc INT INTACK lEI lEO -\IRTxes ._...._... I\ CHANNEL CLOCKS SYNCe WIREOB DTR/REQB RlSB CHANNEL CONTROLS FDOMRAM,OORDEM, Z8030 else __ OTHER z·scc DeDS CH·A CH·B ttt +5V GND PCLK Figure I. Pin Funcllons AD, AD, AD, AD, iNT lEO lEi INTACK +sv WIREQA SYNCA RheA RIlOA TRxCA hDA OTR/REQA RlSA elSA DeCA PClK ADO 39 AD, 38 AD, 37 AD, 36 OS 35 As 34 RIW Z8030 z·scc 11 33 32 31 30 eso es, GND W/REoe 12 29 SYNCe "13 RTxCB 37 RKOB 26 TRlleB 16 25 1)(D8 24 DTRIREQB 18 23 Rlse 19 22 elSS 21 DC De Figure 2. 40-pin Dual-In-Line Package (DIP). Pin Assignments 631 General Description (Continued) The Z-SCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and Synchronous bit-oriented protocols such as HOLC and IBM SOLC. This versatile device supports virtually any serial data transfer application (cassette, diskette, tape drives, etc.). The device can generate and check CRC codes in any Synchronous mode and can be programmed to check data integrity in various modes. The Z-SCC also has facilities for modem controls in both channels. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. The Z-Bus daisy-chain interrupt hierarchy is also supported-as is standard for Zilog peripheral components. The Z8030 Z-SCC is packaged in a 40-pin ceramic DIP and 44-pin chip carrier and uses a single + 5V power supply. ,¢' ~Q'I~Q"~<::>""'t"0"trQ<:>tr<::l"trQ""tr<:>,o(:J? tr1:.:> ,6 5 4 2 1 44434241 40 lEO 7 lEI 8 INTACK 9 ,5V "WIREQA SYNCA 12 AT~CA TRxCA 15 16 NC 17 Z8030 Z·SCC 39 R/W 38 es. 37 es, 36 Ne ONO W/REOB 33 SYNCS 32 R"TxCB 31 RxDB 30 fRiCB TxDB 18 19 20 21 22 23 24 25 26 27 28 ~~f<.?v6¥.d,~~:'~~~~":~~lJ~1f.~~~:f,~iO~CJ Q....~ 1f.~ Figure 2a. 44-pin Chip Carrier. Pin Assignments 632 2016·003 Pin Description The following section describes the pin functions of the Z-SCC. Figures I and 2 detail the respective pin functions and pin assignments. ADo-AD7' Address/Data Bus (bidirectional, active High, 3-state). These multiplexed lines carry register addresses to the Z-SCC as well as data or control information to and from the Z-SCC. AS. Address Strobe (input, active Low). Addresses on ADo-AD? are latched by the rising edge of this signal. CSo. Chip Select 0 (input, active Low). This signal is latched concurrently with the addresses on ADo-AD? and must be active for the intended bus transaction to occur. CS,. Chip Select 1 (input, active High). This second select signal must also be active before the intended bus transaction can occur. CSj must remain active throughout the transaction. CTSA. CTSB. Clear to Send (inputs, active Low). If these pins are programmed as Auto Enables, a Low on the inputs enables their respective transmitters. If not programmed as Auto Enables, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accommodate slow rise-time inputs. The Z-SCC detects pulses on these inputs and can interrupt the CPU on both logic level transitions. DCDA. DCDB. Data Carrier Detect (inputs active Low). These pins f.


Z8030 Z8000 LTA550HQ22


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