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GM71V18163C Dataheets PDF



Part Number GM71V18163C
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 1M-WORDS x 16-BIT CMOS DYNAMIC RAM
Datasheet GM71V18163C DatasheetGM71V18163C Datasheet (PDF)

GM71V18163C GM71VS18163CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description The GM71V(S)18163C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)18163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)18163C/CL offers Extended Data out(EDO) Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)18163C/CL to be packaged in standard 400 mil 42pin plastic SOJ, an.

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GM71V18163C GM71VS18163CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description The GM71V(S)18163C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)18163C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)18163C/CL offers Extended Data out(EDO) Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)18163C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. Features * 1,048,576 Words x 16 Bit Organization * Extended Data Out Mode Capability * Single Power Supply (3.3V+/-0.3V) * Fast Access Time & Cycle Time (Unit: ns) tRAC tCAC GM71V(S)18163C/CL-5 GM71V(S)18163C/CL-6 GM71V(S)18163C/CL-7 50 60 70 13 15 18 tRC 84 104 124 tHPC 20 25 30 Pin Configuration 42 SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 * Low Power Active : 684/612/540mW (MAX) Standby : 7.2mW (CMOS level : MAX) 0.83mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 1024 Refresh Cycles/16ms * 1024 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-version) * 2 CAS byte Control 44(50) TSOP II VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS NC NC WE RAS A11 A10 A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS (Top View) Rev 0.1 / Apr’01 GM71V18163C GM71VS18163CL Pin Description Pin A0-A9 A0-A9 I/O0-I/O15 RAS UCAS, LCAS Function Address Inputs Refresh Address Inputs Data-In/Out Row Address Strobe Column Address Strobe Pin WE OE VCC VSS NC Function Read/Write Enable Output Enable Power (+3.3V) Ground No Connection Ordering Information Type No. GM71V(S)18163CJ/CLJ -5 GM71V(S)18163CJ/CLJ -6 GM71V(S)18163CJ/CLJ -7 GM71V(S)18163CT/CLT -5 GM71V(S)18163CT/CLT -6 GM71V(S)18163CT/CLT -7 Access Time 50ns 60ns 70ns 50ns 60ns 70ns Package 400 Mil 42 Pin Plastic SOJ 400 Mil 44(50) Pin Plastic TSOP II Absolute Maximum Ratings* Symbol TA TSTG VIN/OUT VCC IOUT PD Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin Relative to VSS Supply Voltage Relative to VSS Short Circuit Output Current Power Dissipation Rating 0 ~ 70 -55 ~ 125 -0.5 ~ Vcc+0.5 (<=4.6V(MAX)) -0.5 ~ 4.6 50 1.0 Unit C C V V mA W Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability. Rev 0.1 / Apr’01 GM71V18163C GM71VS18163CL Recommended DC Operating Conditions (TA = 0 ~ 70C) Symbol VCC VIH VIL Parameter Supply Voltage Input High Voltage Input Low Voltage Min 3.0 2.0 -0.3 Typ 3.3 - Max 3.6 VCC + 0.3 0.8 Unit V V V Note: All voltage referred to Vss. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. Truth Table RAS H L L L L L L L L L L L L H to L H to L H to L L L LCAS D L H L L H L L H L L H L H L L H L UCAS D H L L H L L H L L H L L L H L H L WE D H H H L L L L L L H to L H to L H to L D D D D H OE D L L L D D D H H H L to H L to H L to H D D D D H Output Open Valid Valid Valid Open Open Open Undefined Undefined Undefined Valid Valid Valid Open Open Open Open Open Operation Standby Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Lower byte Upper byte Word Word Word Word Word CBR Refresh or Self Refresh (L-series) RAS-only Refresh cycle Read-modify -write cycle Delayed Write cycle Early write cycle Read cycle Notes 1,3 1,3 1,2,3 1,2,3 1,3 1,3 1,3 1,3 Read cycle (Output disabled) Notes: 1. H: High (inactive) L: Low(active) D: H or L 2. tWCS >= 0ns Early write cycle tWCS <= 0ns Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write OPERATION and output High-Z control are done independently by each UCAS,LCAS. ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected. Rev 0.1 / Apr’01 GM71V18163C GM71VS18163CL DC Electrical Characteristics (VCC = 3.3V+/-0.3V, Vss = 0V, TA = 0 ~ 70C) Symbol VOH VOL ICC1 Parameter Output Level Output "H" Level Voltage (IOUT = -2mA) Output Level Output "L" Level Voltage (IOUT = 2mA) Operating Current Average Power Supply Operating Current (RAS, UCAS or LCAS Cycling: tRC = tRC min) Standby Current (TT.


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