PFP13N50

Feb 2009 PFP13N50/PFF13N50 FEATURES ‰ Originative New Design ‰ 100% EAS Test ‰ Rugged Gate Oxide Technology ‰ Extremely Low Intrinsic Capacitances ‰ Remarkable Switching Characteristics ‰ Unequalled Gate Charge : 28 nC (Typ.) ‰ Extended Safe Operating Area ‰ Lower RDS(ON) : 0.46 Ω (Typ.) @VGS=10V APPLICATION ‰ Electronic lamp ballasts based on half bridge topology ‰ PFC (Power Factor Correction) ‰ SMPS (Switched Mode Power Supplies) PFP13N50/PFF13N50 500V N-Channel MOSFET BVDSS = 500 V RDS(on)typ = 0.46 Ω ID = 12.5 A Drain { Gate { ● ◀▲ ● ● Source { TO-220 TO-220F 1 2 3 1.Gate 2. Drain 3. Source 12 3 1.Gate 2. Drain 3. Source Absolute Maximum Ratings TC=25℃ unless otherwise specified Symbol Parameter PFP13N50 PFF13N50 VDSS ID IDM VGS EAS IAR EAR dv/dt Drain-Source Voltage Drain Current Drain Current Drain Current – Continuous (TC = 25℃) – Continuous (TC = 100℃) – Pulsed (Note 1) Gate-Source Voltage Single Pulsed Avalanche Energy (Note 2) Avalanche Current (Note 1) Repetitive Avalanche Energy (Note 1) Peak Diode Recovery dv/dt (Note 3) 500 12.5 12.5* 7.9 7.9* 50 50* ±30 810 12.5 17 5.5 PD Power Dissipation (TC = 25℃) - Derate above 25℃ TJ, TSTG Operating and Storage Temperature Range TL Maximum lead temperature for soldering purposes, 1/8” from case for 5 seconds * Drain current limited by maximum junction temperature 170 56 1.35 0.45 -55 to +150 300 Thermal Resistance Characteristics Symbol RθJC RθCS RθJA Parameter Thermal Resistance, ...