Document
STD4N80K5, STF4N80K5, STP4N80K5, STU4N80K5
N-channel 800 V, 2.1 Ω typ., 3 A Zener-protected SuperMESH™ 5
Power MOSFETs in DPAK, TO-220FP, TO-220 and IPAK packages
Datasheet - production data
TAB
3 1
DPAK
TAB
3 2 1
TO-220FP
TAB
3 2 1
TO-220
IPAK
3
2 1
Figure 1. Internal schematic diagram
'7$%
Features
Order codes VDS RDS(on) max ID
STD4N80K5
STF4N80K5 800 V
STP4N80K5
2.5 Ω
3A
STU4N80K5
• Outstanding RDS(on) * area • Worldwide best FOM (figure of merit) • Ultra low gate charge • 100% avalanche tested • Zener-protected
PTOT 60 W 20 W
60 W
Applications
• Switching applications
* 6
AM01476v1
Description
These N-channel Zener-protected Power MOSFETs are designed using ST’s revolutionary avalanche-rugged very high voltage SuperMESH™ 5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency.
Order code STD4N80K5 STF4N80K5 STP4N80K5 STU4N80K5
Table 1. Device summary
Marking
Packages
4N80K5
DPAK TO-220FP
TO-220 IPAK
Packaging Tape and reel
Tube
December 2013
This is information on a product in full production.
DocID025105 Rev 2
1/23
www.st.com
Contents
Contents
STD4N80K5, STF4N80K5, STP4N80K5, STU4N80K5
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23 DocID025105 Rev 2
STD4N80K5, STF4N80K5, STP4N80K5, STU4N80K5
1 Electrical ratings
Electrical ratings
Symbol
Table 2. Absolute maximum ratings
Value
Parameter
DPAK, IPAK
TO-220FP
TO-220
Unit
VDS Drain-source voltage
VGS Gate- source voltage
ID Drain current (continuous) at TC = 25 °C
ID Drain current (continuous) at TC = 100 °C
(2)
IDM Drain current (pulsed)
PTOT Total dissipation at TC = 25 °C
Avalanche current, repetitive or notIAR repetitive (pulse width limited by TJ max)
EAS
(3)
dv/dt
Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) Peak diode recovery voltage slope
(4)
dv/dt MOSFET dv/dt ruggedness
VISO
Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s, TC = 25 °C)
TJ Operating junction temperature
Tstg Storage temperature
1. Limited by maximum junction temperature
2. Pulse width limited by safe operating area 3. ISD < 3 A, di/dt < 100 A/μs, peak VDS(peak) ≤ V(BR)DSS 4. VDS ≤ 640 V
60
800 ±30
(1)
3
(1)
1.7
(1)
12 20
1
74.5
4.5 50
2500
60
-55 to 150
V A A A W A
mJ V/ns V/ns
V
°C °C
Symbol
Table 3. Thermal data
Parameter
DPAK, IPAK
Value TO-220FP
TO-220
Unit
Rthj-case Thermal resistance junction-case max Rthj-amb Thermal resistance junction-ambient max
(1)
Rthj-pcb Thermal resistance junction-pcb max
1. When mounted on 1inch² FR-4 board, 2 oz Cu
2.08 50
6.25 2.08 62.5
°C/W °C/W °C/W
DocID025105 Rev 2
3/23
23
Electrical characteristics
STD4N80K5, STF4N80K5, STP4N80K5, STU4N80K5
2 Electrical characteristics
(Tcase =25 °C unless otherwise specified)
Symbol
Parameter
Table 4. On /off states Test conditions
Drain-source V(BR)DSS breakdown voltage
ID = 1 mA, VGS = 0
IDSS
IGSS VGS(th) RDS(on)
Zero gate voltage
VDS = 800 V
drain current (VGS = 0) VDS = 800 V, TC=125 °C
Gate-body leakage current (VDS = 0)
VGS = ± 20 V
Gate threshold voltage VDS = VGS, ID = 100 μA
Static drain-source on-
resistance
VGS = 10 V, ID = 1.5 A
Min. Typ. Max. Unit 800 V
1 μA 50 μA ±10 μA 3 4 5V 2.1 2.5 Ω
Symbol
Parameter
Table 5. Dynamic Test conditions
Min. Typ. Max. Unit
Ciss Coss Crss
Input capacitance
Output capacitance
Reverse transfer capacitance
VDS = 100 V, f = 1 MHz, VGS = 0
- 175 - pF - 20 - pF - 1 - pF
(1)
Co(tr)
Equivalent capacitance time related
VDS = 0 to 640 V, VGS = 0
- 26 - pF
Equivalent
(2)
Co(er) capacitance energy related
VDS = 0 to 640 V, VGS = 0
Rg Gate input resistance f=1 MHz, ID = 0
- 11 - pF - 15 - Ω
Qg Total gate charge
VDD = 640 V, ID = 3 A,
Qgs Gate-source charge VGS = 10 V
Qgd Gate-drain charge
(see Figure 19)
- 10.5 - nC - 2 - nC - 7.5 - nC
1. Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
2. Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS
4/23 DocID025105 R.