S3056

DEVICE SMPEUCLITFIIC-RATAIOTEN SONET/SDH CLOCK RECOVERY UNIT BMiUCLMTOI-SRAPTEECLSOCNLEOTC/KSDGHECNLEORCAKTORRECOVERY UNIT ® S3056 S3056 FEATURES SiGe BiCMOS technology Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer and jitter generation On-chip high frequency PLL with internal loop filter for clock recovery Supports clock recovery for: OC-48 (2488.32 Mbps), Fibre Channel (2125 Mbps), OC-24 (1244.16 Mbps), Gigabit Ethernet (1250 Mbps), Fibre Channel (1062.5 Mbps), OC-12 (622.08 Mbps), OC-3 (155.52 Mbps) NRZ data Selectable reference frequencies 19.44 MHz or 155.52 MHz (or equivalent Fibre Channel/ Gigabit Ethernet frequencies) Lock detect—monitors frequency of incoming data Low-jitter serial interface +3.3 V supply Compact 48 pin TQFP TEP package Typical power 620 mW GENERAL DESCRIPTION The function of the S3056 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3056 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figure 1 shows a typical network application. The S3056 receives an OC-48, OC-24, OC-12, OC-3, Fibre Channel or Gigabit Ethernet scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. The S3056 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase relationship between the VCO o...