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GTLP2T152 Dataheets PDF



Part Number GTLP2T152
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description 2-Bit LVTTL/GTLP Transceiver
Datasheet GTLP2T152 DatasheetGTLP2T152 Datasheet (PDF)

GTLP2T152 2-Bit LVTTL/GTLP Transceiver June 2001 Revised February 2002 GTLP2T152 2-Bit LVTTL/GTLP Transceiver General Description The GTLP2T152 is a 2-bit transceiver that provides LVTTLto-GTLP signal level translation. Data directional control is handled with a transmit/receive pin. High-speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fai.

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GTLP2T152 2-Bit LVTTL/GTLP Transceiver June 2001 Revised February 2002 GTLP2T152 2-Bit LVTTL/GTLP Transceiver General Description The GTLP2T152 is a 2-bit transceiver that provides LVTTLto-GTLP signal level translation. Data directional control is handled with a transmit/receive pin. High-speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP’s I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are: VOL = 0.5V, VOH = 1.5V, and VREF = 1V. Features s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA/+24mA s B Port sink +50mA Ordering Code: Order Number GTLP2T152M GTLP2T152MX GTLP2T152K8X Package Number Package Description M08A M08A MAB08A (Preliminary) 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL] Pin Descriptions Pin Names T/R Description LVTTL Direction Control (Receive Direction is Active LOW) Connection Diagrams US8 VCC, GND, VREF Device Supplies An Bn A Port LVTTL Input/Output B Port GTLP Input/Output SOIC © 2002 Fairchild Semiconductor Corporation DS500486 www.fairchildsemi.com GTLP2T152 Functional Description The GTLP2T152 is a 2-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting and the the GTLP/LVTTL outputs are controlled by the T/R pin. Functional Table Inputs Outputs T/R H L Bus An Data to Bus Bn Bus Bn Data to Bus An Bn Output Data Enabled An Output Data Enabled Description Logic Diagram www.fairchildsemi.com 2 GTLP2T152 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V ESD Rating Storage Temperature (TSTG) 100 mA 48 mA −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V Recommended Operating Conditions Supply Voltage VCC Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on A Port and Control Pins HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA) 0.0V to VCC 1.47V to 1.53V 0.98V to 1.02V 3.15V to 3.45V −48 mA −24 mA +24 mA +50 mA −40°C to +85°C −50 mA −50 mA >2000V −65°C to +150°C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VTT VIK VOH A Port B Port Others B Port Others B Port B Port VCC = 3.15V VCC = Min to Max (Note 4) VCC = 3.15V VOL A Port VCC = Min to Max (Note 4) VCC = 3.15V VCC = 3.15V B Port II Control Pins A Port B Port IOFF A Port, Control Pins B Port II (HOLD) IOZH A Port A Port B Port VCC = 0 VCC = 3.15V VCC = 3.45V VI or VO = 0 to 3.45V VI = 0.8V VI = 2.0V VO = 3.45V VO = 3.45V 75 −75 10 5 30 µA VCC = 3.15V VCC = 3.45V VCC = 3.45V VCC = 3.45V VCC = 0 II = −18 mA IOH = −100 µA IOH = −8 mA IOH = -24 mA IOL = 100 µA IOL = 8 mA IOL = 24 mA IOL = 40 mA IOL = 50 mA VI = 3.45V VI = 0V VI = 3.45V VI = 0V VI = 3.45V VI = 0 VI or VO = 0 to 3.45V VCC - 0.2 2.4 2.2 0.2 0.4 0.5 0.4 0.55 5 −5 10 −10 5 −5 30 V µA µA µA µA V V 0.7V VREF + 50 mV 1.0 1.5 Test Conditions Min VREF + 0.05 2.0 0.0 VREF − 0.05 0.8 1.3V VCC −1.2 Typ (Note .


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