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MGA-68563 Dataheets PDF



Part Number MGA-68563
Manufacturers AVAGO
Logo AVAGO
Description Low Noise Amplifier
Datasheet MGA-68563 DatasheetMGA-68563 Datasheet (PDF)

MGA-68563 Current-Adjustable, Low Noise Amplifier Data Sheet Description Avago Technologies MGA-68563 is an economical, easy-to-use GaAs MMIC amplifier that offers excellent linearity and low noise figure for applications from 0.1 to 1.5 GHz. Packaged in an miniature SOT-363 package, it requires half the board space of a SOT-143 package. One external resistor is used to set the bias current from 5mA to 30mA. This allows the designer to use the same part in several circuit positions and tailor t.

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MGA-68563 Current-Adjustable, Low Noise Amplifier Data Sheet Description Avago Technologies MGA-68563 is an economical, easy-to-use GaAs MMIC amplifier that offers excellent linearity and low noise figure for applications from 0.1 to 1.5 GHz. Packaged in an miniature SOT-363 package, it requires half the board space of a SOT-143 package. One external resistor is used to set the bias current from 5mA to 30mA. This allows the designer to use the same part in several circuit positions and tailor the linearity performance (and current consumption) to suit each position. The output of the amplifier is matched to 50Ω (below 2:1 VSWR) across the entire bandwidth and only requires minimum input matching. The amplifier allows a wide dynamic range by offering a 1.0 dB NF coupled with a +20 dBm Output IP3. The circuit uses state-ofthe-art E-pHEMT technology with proven reliability. Onchip bias circuitry allows operation from a single +3V power supply, while internal feedback ensures stability (K>1) over all frequencies for Id at 10mA and above. Features • Single +3V supply • High linearity • Low noise figure • Miniature package • Unconditionally stable Specifications at 500 MHz; 3V, 10 mA (Typ.) • 1.0 dB noise figure • 20 dBm OIP3 • 19.7 dB gain * This represents what Avago Technologies has managed to achieve on a device level with trade off between optimal NF, Gain, OIP3 and input return loss. Applications • LNA for DVB-T,DVB-H, T-DMB, ISDB-T, DAB and MediaFLO Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (CLass 1A) Refer to Agilent Application Note A004R: Electrostatic Discharge Damage and Control. Pin Connections and Package Marking Simplified Schematic Ibias GND 1 GND 2 INPUT 3 6Cx MGA-86563 Pkg 6 OUTPUT and Vd 5 GND 4 BIAS Note: Package marking provides orientation and identification: “6C” = Device Code “x” = Date code indicates the month of manufacture. Rbias Vbias Input match 4 3 Feedback Bias 1, 2, 5 Vd Id = Ids + Ibias Ids 6 MGA-68563 Absolute Maximum Ratings[1] Symbol Vd Id Pin Iref Pdiss TCH TSTG θch_b Parameter Device Voltage (pin 6)[2] Device Current (pin 6)[2] CW RF Input Power (pin 3) [3] Bias Reference Current (pin 4) Total Power Dissipation[4] Channel Temperature Storage Temperature Thermal Resistance[5] Units V mA dBm mA mW °C °C °C/W Absolute Maximum 6 100 21 12 600 150 150 97 Notes: 1. Operation of this device above any one of these parameters may cause permanent damage. 2. Bias is assumed at DC quiescent conditions. 3. With the DC (typical bias) and RF applied to the device at board temperature TB = 25°C. 4. Total dissipation power is referred to lead “5” temperature. Tc=92°C, derate Pdiss at 10.3mW/°C for Tc>92°C. 5. Thermal resistance measured using 150°C Liquid Crystal Measurement method. _ 6Cx + 3V 4300 Ω 10 nF 68 pF 47 nH 100 pF 6.8 nH 4 MGA-68563 3 6 12 5 100 pF Wire Supplying Vbias from Agilent 4142 Direct to Ground RF Output BiBaTsieaes Vdd supply from Agilent 4142 Reference Planes Blocking Cap RF Input Direct to Ground Figure 1a. Test circuit of the 0.5 GHz production test board used for NF, Gain and OIP3 measurements. This circuit achieves a trade-off between optimal NF, Gain, OIP3 and input return loss. Circuit losses have been de-embedded from actual measurements. Figure 1b. A diagram showing the connection to the DUT during an S and Noise parameter measurement using an automated tuner system. 2 MGA-68563 Electrical Specifications TC = 25°C, ZO = 50Ω, Vd = 3V (unless otherwise specified) Symbol Parameters and Test Conditions Freq Id [1,2] NFtest [1,2] Gtest [1,2] OIP3test [1,2] P1dBtest [1,2] Device Current Noise Figure in test circuit [1] f = 0.5 GHz Associated Gain in test circuit [1] f = 0.5 GHz Output 3rd Order Intercept in test circuit [1] f = 0.5 GHz Output Power at 1dB Gain Compression in test circuit. [1] f = 0.5 GHz Units mA dB dB dBm dBm Min. 18 18 Typ. 11 1.0 19.7 20.7 17.5 Max. 16 1.4 21.5 Notes: 1. Guaranteed specifications are 100% tested in the production test circuit, the typical value is based on measurement of at least 600 parts from two non-consecutive wafer lots during initial characterization of this product. 2. Circuit achieved a trade-off between optimal NF, Gain, OIP3 and input return loss. LSL CPK=2.13 USL LSL CPK=3.228 6 7 8 9 10 11 12 13 14 15 16 17 Figure 2. Id @ 3V.LSL=7, Nominal=11, USL=16 CPK=1.62 USL 18 19 20 21 22 Figure 3, OIP3 @ 0.5GHz 3V. LSL=18, Nominal=20.7 LSL CPK=2.276 USL .7 .8 .9 1 1.1 1.2 1.3 1.4 1.5 18 18.5 19 19.5 20 20.5 21 21.5 22 Figure 4. NF @ 0.5GHz 3V.USL=1.4, Nominal=1.0 Figure 5. Gain @ 0.5GHz 3V.USL=18, Nominal=19.7, USL=21.5 Note: Measured on the production circuit. Distribution data sample size is 600 samples taken from 2 non-consecutive wafer lots. Future wafers allocated to this product may have nominal values anywhere between upper and lower limits. 3 MGA-68563 Typical Perf.


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