Document
Philips Semiconductors
TrenchMOS™ transistor Logic level FET
Product specification
PHP45N03LT
FEATURES
• ’Trench’ technology • Very low on-state resistance • Fast switching • Stable off-state characteristics • High thermal cycling performance • Low thermal resistance
SYMBOL
g
d s
QUICK REFERENCE DATA VDSS = 30 V ID = 45 A
RDS(ON) ≤ 24 mΩ (VGS = 5 V) RDS(ON) ≤ 21 mΩ (VGS = 10 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications.
The PHP45N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
PINNING
PIN DESCRIPTION 1 gate 2 drain 3 source tab drain
SOT78 (TO220AB)
tab
1 23
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDGR ±VGS ID ID IDM
Ptot
Tstg, Tj
Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage & operating temperature
-
RGS = 20 kΩ -
Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C -
THERMAL RESISTANCES
SYMBOL Rth j-mb
Rth j-a
PARAMETER
Thermal resistance junction to mounting base Thermal resistance junction to ambient
CONDITIONS -
in free air
MIN.
- 55
MAX.
30 30 15 45 36 180 86 175
UNIT
V V V A A A W ˚C
TYP. -
60
MAX. 1.75
-
UNIT K/W
K/W
November 1997
1
Rev 1.200
Philips Semiconductors
TrenchMOS™ transistor Logic level FET
Product specification
PHP45N03LT
STATIC CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS VGS(TO)
IDSS IGSS RDS(ON)
Drain-source breakdown voltage Gate threshold voltage
Zero gate voltage drain current
Gate source leakage current Drain-source on-state resistance
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C VDS = VGS; ID = 1 mA
Tj = 175˚C Tj = -55˚C
VDS = 30 V; VGS = 0 V;
Tj = 175˚C VGS = ±5 V; VDS = 0 V VGS = 5 V; ID = 25 A VGS = 10 V; ID = 25 A VGS = 5 V; ID = 25 A; Tj = 175˚C
MIN.
30 27 1 0.5 -
TYP.
1.5 0.05 10 20 16 -
MAX.
2 2.3 10 500 100 24 21 45
UNIT
V V V V
µA µA nA mΩ mΩ mΩ
DYNAMIC CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
gfs
Qg(tot) Qgs Qgd
Ciss Coss Crss
td on tr td off tf
Ld
Forward transconductance
Total gate charge Gate-source charge Gate-drain (Miller) charge
Input capacitance Output capacitance Feedback capacitance
Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time
Internal drain inductance
Ld Internal drain inductance
Ls Internal source inductance
CONDITIONS VDS = 25 V; ID = 25 A ID = 40 A; VDD = 24 V; VGS = 5 V
VGS = 0 V; VDS = 25 V; f = 1 MHz
VDD = 15 V; ID = 25 A; VGS = 5 V; RG = 5 Ω Resistive load
Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad
MIN.
8
-
-
-
-
TYP.
16
23 3 12
2000 380 250
30 80 95 40
3.5
MAX.
-
-
2500 450 300
45 130 135 55
-
UNIT
S
nC nC nC
pF pF pF
ns ns ns ns
nH
- 4.5 - nH
- 7.5 - nH
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
IDR Continuous reverse drain current
IDRM Pulsed reverse drain current
VSD Diode forward voltage
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
trr Reverse recovery time IF = 40 A; -dIF/dt = 100 A/µs;
Qrr
Reverse recovery charge
VGS = -10 V; VR = 25 V
MIN. TYP. MAX. UNIT - - 45 A
- - 180 A - 0.95 1.2 V - 1.0 -
- 52 - 0.08 -
ns µC
November 1997
2
Rev 1.200
Philips Semiconductors
TrenchMOS™ transistor Logic level FET
Product specification
PHP45N03LT
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
WDSS
Drain-source non-repetitive unclamped inductive turn-off energy
CONDITIONS
ID = 25 A; VDD ≤ 25 V; VGS = 10 V; RGS = 50 Ω; Tmb = 25 ˚C
MIN. -
TYP. -
MAX. UNIT 60 mJ
November 1997
3
Rev 1.200
Philips Semiconductors
TrenchMOS™ transistor Logic level FET
Product specification
PHP45N03LT
120 PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0 0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
ID% 120 110 100
90 80 70 60 50
Normalised Current Derating
40
30
20
10
0 0
20 40 60 80 100 120 140 160 180 Tmb / C
Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V
ID / A 1000
7528-30
100 RDS(ON) = VDS / ID 10 DC
tp = 10 us 100 us 1 ms 10 ms
1 1 10 100 VDS / V
Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp
Zth j-mb / (K/W) 10
D=
7528-30
1 0.5
0.2
0.1 0.1 0.05
0.02
PD tp
D=
tp T
0 0.01
1E-07
1E-05
1E-03 t/s
T 1E-01
t
1E+01
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
ID / A 80
10
6 60
5
40
VGS / V =
9528-30 4.5
4
3.5
20 3
2.5
0 0 2 4 6 8 10 VD.