Document
CYRS1542AV18
CYRS1544AV18
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology
Radiation Performance
Radiation Data
■ Total Dose =300 Krad
■ Soft error rate (both Heavy Ion and proton) Heavy ions 1 × 10-10 upsets/bit-day with single error correction - double error detection error detection and correction (SEC-DED EDAC)
■ Neutrons = 2.0 × 1014 N/cm2 ■ Dose rate = 2.0 × 109 rad(Si)/sec
■ Dose rate survivability (rad(Si)/sec) = 1.5 × 10^11 rad(Si)/sec ■ Latch up immunity = 120 MeV.cm2/mg (125 °C)
Prototyping Options
■ Non qualified CYPT1542AV18 and CTPY1544AV18 devices with same functional and timing characteristics in a 165-ball Ceramic Column Grid Array (CCGA) package
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 250-MHz clock for high bandwidth
■ 2-word burst on all accesses
■ Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Single multiplexed address input bus latches address inputs for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes ■ QDR® II operates with 2.0 cycle read latency when delay lock
loop (DLL) is enabled
■ Available in × 18 and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD ■ Available in 165-ball CCGA (21 × 25 × 2.83 mm) ■ HSTL inputs and variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ DLL for accurate data placement
Configurations
CYRS1542AV18 – 4 M × 18 CYRS1544AV18 – 2 M × 36
Functional Description
The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.
The QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to turnaround the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words (CYRS1542AV18), or 36-bit words (CYRS1544AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus turnarounds.
Depth.