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W523SXX (PRELIMINARY)
HIGH FIDELITY PowerSpeechTM
GENERAL DESCRIPTION
The W523Sxx family are programmable speech synthesis ICs that utilize Winbond′s new high fidelity voice synthesis algorithm to generate all types of voice effects with high sound quality.
The W523Sxx’ s LOAD, JUMP, MOVE and INC commands and ten programmable registers provide powerful user-programmable functions that make this chip suitable for an extremely wide range of speech IC applications.
The W523Sxx family includes 14 kinds of bodies which are the same except for the voice duration shown below:
PART NO.
W523S08 W523S10 W523S12 W523S15 W523S20 W523S25 W523S30
Duration
8 sec.
10 sec.
12 sec.
15 sec.
20 sec.
25 sec.
30 sec.
PART NO.
Duration
W523S40 40 sec.
W523S50 50 sec.
W523S60 60 sec.
W523S70 70 sec.
W523S80 80 sec.
W523S99 W523M02 100 sec. 120 sec.
Note: The voice duration is estimated by 6.4 KHz sampling rate.
FEATURES
• Operating voltage range: 2.4 – 5.5 volts for both DAC and PWM output • New high fidelity synthesis algorithm • Either PWM mode or D/A converter mode can be selected for AUD output • Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs • Two trigger input debounce times (50 mS or 400 uS) can be set • Provides up to 2 LEDs and 5 STOP outputs • Flexible functions programmable through the following:
− LD (Load), JP (Jump), MV (Move) and INC (Increase) commands − Four general purpose registers: R0, R1, R2 and R3 − Six special purpose registers: EN0, EN1, MODE0, MODE1, STOP and PAGE − Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6 − Speech equations − END instruction • Supports CPU interface operation • Symbolic compiler supported • Instruction cycle ≤ 400 µS typically • Section control for − Variable frequency: 4.8/6/8/12 KHz
Publication Release Date:Oct. 2000 - 1 - Revision A5
W523SXX (PRELIMINARY)
− LED: ON/OFF • Up to 256 voice groups can be used in single page mode; or extended to 2,048 voice groups
in multi page mode, such as 8-page, 16-page and 32-page.
BLOCK DIAGRAM
OSC
VDD1 RESET
TEST TG1 TG2 TG5 TG6
VSS1 LED1
TIMING GENERATOR CONTROLLER
ROM
SPEECH SYNTHESIZER
PWM DRIVER D/A CONVERTER
SPK-
SPK+/AUD
VDD2 VSS2
STPE STPD LED2/STPC STPB STPA/BUSY
PIN DESCRIPTION
-2-
W523SXX (PRELIMINARY)
NAME OSC VDD1 TEST
RESET TG1 TG2 TG5 TG6 VSS1 LED1 STPA/BUSY STPB LED2/STPC STPD STPE SPKAUD/SPK+ VSS2 VDD2
I/O DESCRIPTION I Ring oscillator input - Positive power supply I Test pin. Internally pulled low I Active low to reset all devices as POR function. Internally pulled high.
I Direct trigger input 1. Internally pulled high I Direct trigger input 2. Internally pulled high I Direct trigger input 5. Internally pulled high I Direct trigger input 6. Internally pulled high - Negative power supply O LED1 output O Stop signal A or Busy signal O Stop signal B O LED2 output or Stop signal C O Stop signal D O Stop signal E O PWM output O Current type output or PWM output for speaker - Negative power supply - Positive power supply
FUNCTIONAL DESCRIPTION
I/O pins:
The W523Sxx family provides up to 4 trigger pins, which can be extended to 24 matrix trigger inputs, up to 5 STOP output pins and up to 2 LED output pins. All of these I/O pins’ status can be easily defined by PowerSpeech™ program. Powerful programmable features:
The W523Sxx family provides JUMP (JP), LOAD (LD), MOVE (MV), INC, and END commands and 10 programmable registers, such as R0 ~ R3, EN0, EN1, MODE0, MODE1, STOP and PAGE, can be easily used to program the desired playing mode, stop output signal form, LED flash type, and trigger pin interrupt modes. The chip’ s programmable features can also be used to develop new, customized functions for a wide variety of innovative applications.
Programmable Power-on Initialization:
Whenever the W523Sxx is powered on or pressed the RESET pin, the program contained in the 32nd voice group will be executed after the power-on delay (about 160 mS), so the user can write a program into this group to set the power-on initial state. If user does not wish to execute a program at
Publication Release Date: Oct 2000 - 3 - Revision A5
W523SXX (PRELIMINARY)
power-on, an “ END” instruction should be entered in the group 32.
The interruption priority is shown as below while other trigger pins as well as JUMP (JP) command are executing simultaneously during POI executing period:
POI > TG1F > TG1R > TG2F > TG2R > TG5F > TG5R > TG6F > TG6R > "JP" instruction.
Register Definition and Control
The register file in the W523Sxx family is composed of 10 registers, including 4 general-purpose registers and 6 special purpose registers. They are defined to facilitate the operations for various purposes. The default setting values of the registers are given in the following table.
REGISTER
NAME
DEFAULT SETTING
General Register
R0-R3
00100000B
Special Register
EN0
XX11XX11B
EN1 XX11XX11B
MODE0, MODE1
11111111B
STOP
XXX11111B
PAGE.