AS7C4096

January 2001 AS7C4096 AS7C34096 ® 5V/3.3V 512K × 8 CMOS SRAM Features AS7C4096 (5V version) AS7C34096 (3.3V version) Industrial and commercial temperature Organization: 524,288 words × 8 bits Center power and ground pins High speed - 10/12/15/20 ns address access time - 5/6/7/9 ns output enable access time Low power consumption: ACTIVE - 1375 mW (AS7C4096) / max @ 12 ns - 468 mW (AS7C34096) / max @ 12 ns Low power consumption: STANDBY - 110 mW (AS7C4096) / max CMOS - 72 mW (AS7C34096) / max CMOS 2.0V data retention Equal access and cycle times Easy memory expansion with CE, OE inputs TTL-compatible, three-state I/O JEDEC standard packages - 400 mil 36-pin SOJ - 400 mil 44-pin TSOP II ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA Row decoder Sense amp Logic block diagram VCC GND Input buffer A0 A1 A2 A3 524,288 × 8 A4 A5 Array A6 (4,194,304) A7 A8 A9 Column decoder Control Circuit I/O1 I/O8 WE OE CE Pin arrangement 36-pin SOJ (400 mil) 44-pin TSOPII(400 mil) A0 A1 A2 A3 A4 CE I/O1 I/O2 GVNCDC I/O3 I/O4 WE A5 A6 A7 A8 A9 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 24 14 23 15 22 16 21 17 20 18 19 NC 1 44 NC A18 A17 A16 A15 OE I/O8 I/O7 GND VCC I/O6 I/O5 A14 A13 A12 A11 A10 NC NC A0 A1 A2 A3 A4 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A5 A6 A7 A8 A9 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 NC 21 24 NC 22 23 NC NC NC A18 A17 A16 A15 ...