CS18LV40963

High Speed Super Low Power SRAM 512K Word By 8 Bit CS18LV40963 Revision History Rev. No. 2.0 2.1 History Initial issue with new naming rule Add a new 32L WSON –8x8mm package Issue Date Jan.26, 2005 Aug.12, 2005 1 Rev. 2.1 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 512K Word By 8 Bit CS18LV40963 GENERAL DESCRIPTION The CS18LV40963 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 524,288 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE) and three-state output drivers. The CS18LV40963 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV40963 is available in JEDEC standard 32-pin sTSOP 1 -8x13.4 mm, TSOP 1 -8x20mm, TSOP 2 -400mil, SOP -450 mil and WSON –8x8mm packages. . FEATURES Low operation voltage : 2.7 ~ 3.6V Ultra low power consumption : 3mA＠1MHz (Max.) operating current 0.50 uA (Typ.) CMOS standby current High speed access time : 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible Data retention s...