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MPC92432 Dataheets PDF



Part Number MPC92432
Manufacturers Motorola
Logo Motorola
Description 1360 MHz Dual Output LVPECL Clock Synthesizer
Datasheet MPC92432 DatasheetMPC92432 Datasheet (PDF)

Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MPC92432 Rev 0, 06/2004 Product Preview 1360 MHz Dual Output LVPECL Clock Synthesizer The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 21.25 MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of t.

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Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MPC92432 Rev 0, 06/2004 Product Preview 1360 MHz Dual Output LVPECL Clock Synthesizer The MPC92432 is a 3.3V compatible, PLL based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking, and computing applications. With output frequencies from 21.25 MHz to 1360 MHz and the support of two differential PECL output signals, the device meets the needs of the most demanding clock applications. Features MPC92432 1360 MHz LOW VOLTAGE CLOCK SYNTHESIZER Freescale Semiconductor, Inc... • • • • • • • • • • • • • 21.25 MHz to 1360 MHz synthesized clock output signal Two differential, LVPECL-compatible high-frequency outputs Output frequency programmable through 2-wire I2C bus or parallel interface On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock input Synchronous clock stop functionality for both outputs LOCK indicator output (LVCMOS) LVCMOS compatible control inputs Fully integrated PLL 3.3-V power supply 48-lead LQFP SiGe Technology Ambient temperature range: –40°C to +85°C SCALE 2:1 FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932 Applications • Programmable clock source for server, computing, and telecommunication systems • Frequency margining • Oscillator replacement Functional Description The MPC92432 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can be changed on the fly for frequency margining purpose. The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2720 MHz. Its output is scaled by a divider that is configured by either the I2C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL is internal. The PLL post-divider N is configured through either the I2C or the parallel interfaces, and can provide one of six division ratios (2, 4, 8, 16, 32, 64). This divider extends the performance of the part while providing a 50% duty cycle. The high-frequency outputs, QA and QB, are differential and are capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The second high-frequency output, QB, can be configured to run at either 1x or 1/2x of the clock frequency or the first output (QA). The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. The configuration logic has two sections: I2C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB, and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I2C interface. The serial interface is I2C compatible and provides read and write access to the internal PLL configuration registers. The lock state of the PLL is indicated by the LVCMOS-compatible LOCK outputs. This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC92432 REF_CLK XTAL1 XTAL2 REF_SEL TEST_EN SDA SCL ADR[1:0] PLOAD M[9:0] NA[2:0] NB P CLK_STOPx BYPASS MR XTAL fREF ÷P PLL fVCO ÷NA fQA QA fQB ÷NB QB ÷M PLL Configuration Registers I2C Control LOCK Freescale Semiconductor, Inc... Figure 1. MPC92432 — Generic Logic Diagram TEST_EN 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 27 GND NA2 NA1 NA0 PLOAD VCC MR SDA SCL ADR1 ADR0 P LOCK 26 GND GND VCC VCC VCC QA QA QB QB NB 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 M9 M8 M7 M6 M5 GND M4 M3 M2 M1 M0 VCC MPC92432 18 17 16 15 14 13 CLK_STOPA CLK_STOPB It is recommended to use an external RC filter for the analog VCC_PLL supply pin. Please see the application section for details. REF_CLK BYPASS VCC VCC GND REF_SEL GND XTAL1 2 MOTOROLA VCC_PLL Figure 2. 48-Lead Package Pinout (Top View) TIMING SOLUTIONS For More Information On This Product, Go to: www.freescale.com XTAL2 Freescale Semiconductor, Inc. MPC92432 Table 1. Signal Configuration Pin XTAL1, XTAL2 REF_CLK REF_SEL QA QB LOCK M[9:0] NA[2:0] NB I/O Input Input Input Output Output Output Input Input Input Input Input I/O Input Input Input Input Input Input Supply Supply Analog LVCMOS LVCMOS Differential LVPEC.


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