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IRFBC30S Dataheets PDF



Part Number IRFBC30S
Manufacturers Vishay
Logo Vishay
Description Power MOSFET
Datasheet IRFBC30S DatasheetIRFBC30S Datasheet (PDF)

IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 31 4.6 17 Single D FEATURES 600 2.2 • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount (IRFBC30S, SiHFBC30S) • Low-Profile Through-Hole (IRFBC30L, SiHFBC30L) • Available in Tape and Reel (IRFBC30S, SiHFBC30S) • Dynamic dV/dt Rating • 150 °C Operating Temperature • Fast Switching • Fully Avalanche Rated • Complia.

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IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 31 4.6 17 Single D FEATURES 600 2.2 • Halogen-free According to IEC 61249-2-21 Definition • Surface Mount (IRFBC30S, SiHFBC30S) • Low-Profile Through-Hole (IRFBC30L, SiHFBC30L) • Available in Tape and Reel (IRFBC30S, SiHFBC30S) • Dynamic dV/dt Rating • 150 °C Operating Temperature • Fast Switching • Fully Avalanche Rated • Compliant to RoHS Directive 2002/95/EC Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK is a surface mount power package capable of the accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (IRFBC30L, SiHFBC30L) is a available for low-profile applications. D2PAK (TO-263) SiHFBC30STRL-GE3a IRFBC30STRLPbFa SiHFBC30STL-E3a I2PAK (TO-262) SiHFBC30L-GE3 IRFBC30LPbF SiHFBC30L-E3 I2PAK (TO-262) D2PAK (TO-263) DESCRIPTION G G D S G D S S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free and Halogen-free Lead (Pb)-free Note a. See device orientation. D2PAK (TO-263) SiHFBC30S-GE3 IRFBC30SPbF SiHFBC30S-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Currente Pulsed Drain Linear Derating Factor Single Pulse Avalanche Energyb, e Avalanche Currenta Repetiitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) dV/dtc, e TA = 25 °C TC = 25 °C Currenta, e VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg for 10 s LIMIT 600 ± 20 3.6 2.3 14 0.59 290 3.6 7.4 3.1 74 3.0 - 55 to + 150 300d UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V, starting TJ = 25 °C, L = 41 mH, Rg = 25 , IAS = 3.6 A (see fig. 12). c. ISD  3.6 A, dI/dt  60 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. Uses IRFBC30, SiHFBC30 data and test conditions. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91111 S11-1053-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC30S, SiHFBC30S, IRFBC30L, SiHFBC30L Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient (PCB Mounted, steady-state)a Maximum Junction-to-Case (Drain) SYMBOL RthJA RthJC TYP. MAX. 40 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). For recommended footprint and soldering techniques refer to application note #AN-994. SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf LS VGS = 0, ID = 250 μA Reference to 25 °C, ID = 1 VGS = ± 20 V VDS = 600 V, VGS = 0 V VDS = 480 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 2.2 Ab Ac VDS = 50 V, ID = 2.2 mAc VDS = VGS, ID = 250 μA 600 2.0 2.5 0.62 - 4.0 ± 100 100 500 2.2 - V V/°C V nA μA  S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5c - 660 86 19 11 13 35 14 7.5 31 4.6 17 nH ns nC pF VGS = 10 V ID = 3.6 A, VDS = 360 V, see fig. 6 and 13b, c - VDD = 300 V, ID = 3.6 A, Rg = 12 , RD = 82 , see fig. 10b, c - Between lead, and center of die contcat - - 370 2.0 3.6 A 14 1.6 810 4.2 V ns μC G S TJ = 25 °C, IS = 3.6 A, VGS = 0 Vb TJ = 25 °C, IF = 3.6 A, dI/dt = 100 A/μsb, c Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; dut.


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