Document
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4264405, 42S65405, 4265405
64 M-BIT DYNAMIC RAM 16 M-WORD BY 4-BIT, EDO
Description
The µPD4264405, 42S65405, 4265405 are 16,777,216 words by 4 bits CMOS dynamic RAMs with optional EDO. EDO is a kind of the page mode and is useful for the read operation. Besides, the µPD42S65405 can execute CAS before RAS self refresh. These are packaged in 32-pin plastic TSOP (II) and 32-pin plastic SOJ.
Features
• EDO (Hyper page mode) • 16,777,216 words by 4 bits organization • Single +3.3 V ± 0.3 V power supply • Fast access and cycle time
Part number
Power consumption Active (MAX.) 360 mW
Access time (MAX.) 50 ns
R/W cycle time (MIN.) 84 ns
EDO (Hyper page mode) cycle time (MIN.) 20 ns
µPD4264405-A50 µPD42S65405-A50, 4265405-A50 µPD4264405-A60 µPD42S65405-A60, 4265405-A60
468 mW 324 mW 396 mW 60 ns 104 ns 25 ns
• The µPD42S65405 can execute CAS before RAS self refresh.
Part number Refrech cycle 4,096 cycles/128 ms Refresh RAS only refresh, Normal read/write, CAS before RAS self refresh, CAS before RAS refresh, Hidden refresh RAS only refresh, Normal read/write CAS before RAS refresh, Hidden refresh RAS only refresh, Normal read/write, CAS before RAS refresh, Hidden refresh Power consumption at standby (MAX.) 0.72 mW (CMOS level input) 1.8 mW (CMOS level input)
µPD42S65405
µPD4264405
8,192 cycles/64 ms 4,096 cycles/64 ms
µPD4265405
4,096 cycles/64 ms
The information in this document is subject to change without notice. Document No. M10856EJ6V0DS00 (6th edition) Date Published September 1997 N Printed in Japan
The mark
shows major revised points.
©
1995
µPD4264405, 42S65405, 4265405
Ordering Information
Access time (MAX.) 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 32-pin plastic SOJ (400 mil)
Part number
Package 32-pin plastic TSOP (II) (400 mil) 32-pin plastic SOJ (400 mil) 32-pin plastic TSOP (II) (400 mil)
Refresh CAS before RAS self refresh CAS before RAS refresh RAS only refresh Hidden refresh CAS before RAS refresh RAS only refresh Hidden refresh
µPD42S65405G5-A50-7JD µPD42S65405G5-A60-7JD µPD42S65405LE-A50 µPD42S65405LE-A60 µPD4264405G5-A50-7JD µPD4264405G5-A60-7JD µPD4265405G5-A50-7JD µPD4265405G5-A60-7JD µPD4264405LE-A50 µPD4264405LE-A60 µPD4265405LE-A50 µPD4265405LE-A60
2
µPD4264405, 42S65405, 4265405
Pin Configurations (Marking Side)
32-pin Plastic TSOP (II) (400 mil) 32-pin Plastic SOJ (400 mil)
µ PD4264405G5-7JD µ PD42S65405G5-7JD µ PD4265405G5-7JD
µ PD4264405LE µ PD42S65405LE µ PD4265405LE
VCC I/O1 I/O2 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
GND I/O4 I/O3 NC NC NC CAS OE A12/NC A11 A10 A9 A8 A7 A6 GND
Note
VCC I/O1 I/O2 NC NC NC NC WE RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
GND I/O4 I/O3 NC NC NC CAS OE A12/NC A11 A10 A9 A8 A7 A6 GND
Note
Note A12 ... µ PD4264405 NC ... µ PD42S65405, 4265405 A0 to A12 RAS CAS WE OE V CC GND NC : Address Inputs : Row Address Strobe : Column Address Strobe : Write Enable : Output Enable : Power Supply : Ground : No Connection
I/O1 to I/O4 : Data Inputs/Outputs
3
µPD4264405, 42S65405, 4265405
Block Diagram
RAS CAS WE Data Output Buffer Clock Generator OE
VCC GND
CAS before RAS Counter
Row Decoder
Memory Cell Array Bit organizationNote2
I/O1 to I/O4
Row Address Buffer AddressNote 1 Column Address Buffer Column Decoder Sense Amplifier ×4
Data Input Buffer
Notes 1.
Part number
Row address A0 - A12 A0 - A11
Column address A0 - A10 A0 - A11
µPD4264405 µPD42S65405, 4265405
2. 4,096 × 4,096 × 4
4
µPD4264405, 42S65405, 4265405
Input/Output Pin Functions
The µPD4264405, 42S65405, 4265405 have input pins RAS, CAS, WE, OE, AddressNote and input/output pins I/O1 to I/O4.
Pin name RAS (Row address strobe)
Input/Output Input
Function RAS activates the sense amplifier by latching a row address and selecting a corresponding word line. It refreshes memory cell array of one line selected by the row address. It also selects the following function. • CAS before RAS self refresh, CAS before RAS refresh CAS activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. Address bus. Input total 24-bit of address signal, upper bits and lower bitsNote in sequence (address multiplex method). Therefore, one word is selected from 16,777,216-word by 4-bit memory cell array. In actual operation, latch row address by specifying row address and activating RAS. Then, switch the address bus to column address and activate CAS. Each address is taken into the device when RAS and CAS are activated. Therefore, the address input setup time (tASR, tASC) and hold time (tRAH, tCAH) are specified for the activation of RAS and CAS. Write control signal. Write operation is executed by activating RAS, CAS and WE. Read control signal. Read operation can be executed by activating.