NT5CB512M4BN

2Gb DDR3 SDRAM B-Die NT5CB512M4BN / NT5CB256M8BN / NT5CB128M16BP NT5CC512M4BN / NT5CC256M8BN / NT5CC128M16BP Feature  1.5V ± 0.075V / 1.35V -0.0675V/+0.1V (JEDEC        Write Leveling OCD Calibration Dynamic ODT (Rtt_Nom & Rtt_WR) Auto Self-Refresh Self-Refresh Temperature RoHS compliance and Halogen free Packages: Standard Power Supply)         8 Internal memory banks (BA0- BA2) Differential clock input (CK, ) Programmable  Latency: 6, 7, 8, 9, 10, 11 Programmable Additive Latency: 0, CL-1, CL-2 Programmable Sequential / Interleave Burst Type Programmable Burst Length: 4, 8 8 bit prefetch architecture Output Driver Impedance Control 78-Ball BGA for x4 & x8 components 96-Ball BGA for x16 components Description The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 2,147,483,648 bits. It is internally configured as an octal-bank DRAM. The 2Gb chip is organized as 64Mbit x 4 I/O x 8 bank, 32Mbit x 8 I/O x 8 bank or 16Mbit x 16 I/O x 8 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair ...