STS3623

S amHop Microelectronics C orp. S T S 3623 J un, 09 2006 Dual N-Channel Enhancement Mode Field Effect Transistor P R ODUC T S UMMAR Y V DS S 30V F E AT UR E S S uper high dense cell design for low R DS (ON ). ID 4A R DS (ON) ( m : ) Max 50 @ V G S = 10V 65 @ V G S = 4.5V R ugged and reliable. S OT-26 package. D1 D2 S OT26 Top View G1 S2 G2 1 2 3 6 5 4 D1 S1 D2 G1 S1 G2 S2 AB S OL UTE MAXIMUM R ATINGS (T A =25 C unles s otherwis e noted) P arameter Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous @ T J =25 C b -P ulsed Drain-S ource Diode Forward C urrent Maximum P ower Dissipation a Operating Junction and S torage Temperature R ange S ymbol V DS V GS ID IDM IS PD T J , T S TG Limit 30 20 4 16 1.25 1.25 -55 to 150 Unit V V A A A W C THE R MAL CHAR ACTE R IS TICS Thermal R esistance, Junction-to-Ambient a R thJA 100 C /W 1 S T S 3623 E LE CTR ICAL CHAR ACTE R IS TICS (T A =25 C unless otherwise noted) Parameter OFF CHAR ACTE R IS TICS Drain-S ource Breakdown Voltage Zero Gate Voltage Drain Current Gate-Body Leakage BV DS S IDS S IGS S V GS (th) R DS (ON) ID(ON) gFS c S ymbol Condition V GS = 0V, ID = 250uA V DS = 24V, V GS = 0V V GS = 20V, V DS = 0V V DS = V GS , ID = 250uA V GS = 10V, ID = 3A V GS = 4.5V, ID = 2A V DS = 5V, V GS = 4.5V V DS = 5V, ID =3A Min Typ C Max Unit 30 1 100 1 1.6 40 50 10 7 280 70 38 3 50 65 V uA nA V m-ohm m-ohm ON CHAR ACTE R IS TICS b Gate Threshold Voltage Drain-S ource On-S tate R esistance On-S tate Drain ...