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H5MS2562JFR-J3M Dataheets PDF



Part Number H5MS2562JFR-J3M
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description Mobile DDR SDRAM 256Mbit (16M x 16bit)
Datasheet H5MS2562JFR-J3M DatasheetH5MS2562JFR-J3M Datasheet (PDF)

256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb (16Mx16bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / July. 2009 1 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM Rev.

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256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Specification of 256Mb (16Mx16bit) Mobile DDR SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / July. 2009 1 256Mbit MOBILE DDR SDRAM based on 4M x 4Bank x16 I/O Document Title 256Mbit (4Bank x 4M x 16bits) MOBILE DDR SDRAM Revision History Revision No. 0.1 0.2 1.0 1.1 1.2 - Initial Draft - IDD Specification updated - The final version - Insert DDR370 DC/AC Characteristics - Omit a typo in package information History Draft Date May 2008 May 2008 Nov. 2008 Apr. 2009 July. 2009 Remark Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / July. 2009 2 Mobile DDR SDRAM 256Mbit (16M x 16bit) H5MS2562JFR Series FEATURES SUMMARY ● Mobile DDR SDRAM clock cycle ● MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ - Keep to the JEDEC Standard regulation (Low Power DDR SDRAM) - Double data rate architecture: two data transfer per ● Mobile DDR SDRAM INTERFACE - x16 bus width - Multiplexed Address (Row address and Column address) ● CAS LATENCY - Programmable CAS latency 2 or 3 supported ● SUPPLY VOLTAGE - 1.8V device: VDD and VDDQ = 1.7V to 1.95V ● BURST LENGTH - Programmable burst length 2 / 4 / 8 with both sequential and interleave mode ● MEMORY CELL ARRAY - 256Mbit (x16 device) = 4M x 4Bank x 16 I/O ● AUTO PRECHARGE - Option for each burst access ● DATA STROBE - x16 device: LDQS and UDQS - Bidirectional, data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - Data and data mask referenced to both edges of DQS ● AUTO REFRESH AND SELF REFRESH MODE ● CLOCK STOP MODE - Clock stop mode is a feature supported by Mobile DDR SDRAM. - Keep to the JEDEC Standard regulation ● LOW POWER FEATURES - PASR (Partial Array Self Refresh) - AUTO TCSR (Temperature Compensated Self Refresh) - DS (Drive Strength) - DPD (Deep Power Down): DPD is an optional feature, so please contact Hynix office for the DPD feature ● INITIALIZING THE MOBILE DDR SDRAM - Occurring at device power up or interruption of device power ● PACKAGE - H5MS2562JFR: 60 Ball FBGA, Lead & Halogen free ● INPUT CLOCK - Differential clock inputs (CK, CK) ● This product is in compliance with the directive pertaining of RoHS. ● Data MASK - LDM and UDM: Input mask signals for write data - DM masks write data-in at the both rising and falling edges of the data strobe Rev 1.2 / July. 2009 3 Mobile DDR SDRAM 256Mbit (16M x 16bit) H5MS2562JFR Series DESCRIPTION The Hynix H5MS2562JFR Series is 268,435,456-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 4,194,304 x16. The HYNIX H5MS2562JFR series uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data per clock cycle at the I/O pins. The Hynix H5MS2562JFR Series offers fully synchronous operations referenced to both rising and falling edges of the clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates from a differential clock: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK), data, data strobe and data mask inputs are sampled on both rising and falling edges of it (Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). The data paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible with LVCMOS. Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 locations. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burs.


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