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AS7C34098 Dataheets PDF



Part Number AS7C34098
Manufacturers Alliance Semiconductor
Logo Alliance Semiconductor
Description 5V/3.3V 256K x 16 CMOS SRAM
Datasheet AS7C34098 DatasheetAS7C34098 Datasheet (PDF)

March 2002 ® AS7C4098 AS7C34098 5V/3.3V 256K × 16 CMOS SRAM Features • AS7C4098 (5V version) • AS7C34098 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: STANDBY - 110 mW (AS7C4098)/max CMOS - 72 mW (AS7C34098)/max CMOS • Individual byte read/write controls • Easy memory expansion with CE, OE inputs • TT.

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March 2002 ® AS7C4098 AS7C34098 5V/3.3V 256K × 16 CMOS SRAM Features • AS7C4098 (5V version) • AS7C34098 (3.3V version) • Industrial and commercial temperature • Organization: 262,144 words × 16 bits • Center power and ground pins • High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time • Low power consumption: STANDBY - 110 mW (AS7C4098)/max CMOS - 72 mW (AS7C34098)/max CMOS • Individual byte read/write controls • Easy memory expansion with CE, OE inputs • TTL- and CMOS-compatible, three-state I/O • 44-pin JEDEC standard packages - 400-mil SOJ - TSOP 2 - 48-ball FBGA 7 x 11 mm • Low power consumption: ACTIVE - 1375 mW (AS7C4098)/max @ 12 ns - 468 mW (AS7C34098)/max @ 12 ns • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 WE VCC 1024 × 256 × 16 Array (4,194,304) GND Pin arrangement for SOJ and TSOP 2 44-pin (400 mil) SOJ TSOP2 Row Decoder I/O buffer Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17 UB OE LB CE A0 A1 A2 A3 A4 CE I/O1 I/O2 I/O3 I/O4 VCC GND I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 Selection guide –10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C4098 AS7C34098 AS7C4098 AS7C34098 10 5 – 160 – 20 –12 12 6 250 130 20 20 –15 15 7 220 110 20 20 –20 20 9 180 100 20 20 Unit ns ns mA mA mA mA 5/23/02; v.1.8 Alliance Semiconductor P. 1 of 12 Copyright © Alliance Semiconductor. All rights reserved. AS7C4098 AS7C34098 ® Ball arrangement BGA 48-BGA Ball-Grid-Array Package A B C D E F G H 1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 NC 2 OE UB I/O11 I/O12 I/O13 I/O14 NC A8 3 A0 A3 A5 A17 NC A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O2 I/O4 I/O5 I/O6 WE A11 6 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC 48-BGA Ball-Grid-Array Package Version 2 Alternative 1 A LB B I/O1 C I/O2 D VSS E VCC F I/O7 G I/O8 H NC 2 3 4 5 6 OE A0 A1 A2 NC UB A3 A4 CE I/O9 I/O3 A5 A6 I/O11 I/O10 I/O4 A17 A7 I/O12 VCC I/O5 NC A16 I/O13 VSS I/O6 A14 A15 I/O14 I/O15 NC A12 A13 WE I/O16 A8 A9 A10 A11 NC 5/23/02; v.1.8 Alliance Semiconductor P. 2 of 12 AS7C4098 AS7C34098 ® Functional description The AS7C4098 and AS7C34098 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices organized as 262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems. When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 110 mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16. All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V (AS7C34098) supply. Both devices are available in the JEDEC standard 400-mL, 44-pin SOJ, TSOP 2, and 48 - CSP/BGA packages. Absolute maximum ratings Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Device AS7C4098 AS7C34098 Symbol Vt1 Vt1 Vt2 PD Tstg Tbias IOUT Min –0.50 –0.50 –0.50 – –65 –55 – Max +7.0 +5.0 VCC +0.50 1.5 +150 +125 ±20 Unit V V V W °C °C mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabi.


AS7C4098 AS7C34098 ZAPD-2


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