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SSM3K324R Dataheets PDF



Part Number SSM3K324R
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description Silicon N-Channel MOSFET
Datasheet SSM3K324R DatasheetSSM3K324R Datasheet (PDF)

MOSFETs Silicon N-Channel MOS SSM3K324R 1. Applications • Power Management Switches • DC-DC Converters 2. Features (1) 1.8-V gate drive voltage. (2) Low drain-source on-resistance : RDS(ON) = 56 mΩ (max) (@VGS = 4.5 V) RDS(ON) = 72 mΩ (max) (@VGS = 2.5 V) RDS(ON) = 109 mΩ (max) (@VGS = 1.8 V) 3. Packaging and Pin Assignment SOT-23F SSM3K324R 1: Gate 2: Source 3: Drain ©2021 1 Toshiba Electronic Devices & Storage Corporation Start of commercial production 2012-10 2021-09-14 Rev.3.0 SSM3K324.

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MOSFETs Silicon N-Channel MOS SSM3K324R 1. Applications • Power Management Switches • DC-DC Converters 2. Features (1) 1.8-V gate drive voltage. (2) Low drain-source on-resistance : RDS(ON) = 56 mΩ (max) (@VGS = 4.5 V) RDS(ON) = 72 mΩ (max) (@VGS = 2.5 V) RDS(ON) = 109 mΩ (max) (@VGS = 1.8 V) 3. Packaging and Pin Assignment SOT-23F SSM3K324R 1: Gate 2: Source 3: Drain ©2021 1 Toshiba Electronic Devices & Storage Corporation Start of commercial production 2012-10 2021-09-14 Rev.3.0 SSM3K324R 4. Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta = 25 �) Characteristics Symbol Rating Unit Drain-source voltage Gate-source voltage VDSS 30 V VGSS ± 12 Drain current (DC) (Note 1) ID 4.0 A Drain current (pulsed) (Note 1), (Note 2) IDP 10 Power dissipation Power dissipation Channel temperature (Note 3) PD (t ≤ 10 s) (Note 3) PD Tch 1 W 2 150 � Storage temperature Tstg -55 to 150 Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 1: Ensure that the channel temperature does not exceed 150 �. Note 2: Pulse width (PW) ≤ 10 ms, duty ≤ 1% Note 3: Device mounted on an FR4 board. (25.4 mm × 25.4 mm × 1.6 mm ,Cu pad: 645 mm2) Note: Note: The MOSFETs in this device are sensitive to electrostatic discharge. When handling this device, the worktables, operators, soldering irons and other objects should be protected against anti-static discharge. The channel-to-ambient thermal resistance, Rth(ch-a), and the drain power dissipation, PD, vary according to the board material, board area, board thickness and pad area. When using this device, be sure to take heat dissipation fully into account. ©2021 2 Toshiba Electronic Devices & Storage Corporation 2021-09-14 Rev.3.0 SSM3K324R 5. Electrical Characteristics 5.1. Static Characteristics (Unless otherwise specified, Ta = 25 �) Characteristics Symbol Test Condition Min Typ. Max Unit Gate leakage current Drain cut-off current Drain-source breakdown voltage Drain-source breakdown voltage Gate threshold voltage Drain-source on-resistance Forward transfer admittance IGSS VGS = ± 10 V, VDS = 0 V IDSS VDS = 24 V, VGS = 0 V V(BR)DSS ID = 1 mA, VGS = 0 V (Note 1) V(BR)DSX ID = 1 mA, VGS = -12 V (Note 2) Vth VDS = 3 V, ID = 1 mA (Note 3) RDS(ON) ID = 2.0 A, VGS = 4.5 V ID = 1.0 A, VGS = 2.5 V ID = 0.5 A, VGS = 1.8 V (Note 3) |Yfs| VDS = 3 V, ID = 2.0 A � � ± 10 µA � � 1 30 � � V 18 � � 0.4 � 1.0 � 45 56 mΩ � 55 72 � 69 109 � 10.5 � S Note 1: If a reverse bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the drainsource breakdown voltage is lowered in this mode. Note 2: Let Vth be the voltage applied between gate and source that causes the drain current (ID) to below (1 mA for this device). Then, for normal switching operation, VGS(ON) must be higher than Vth, and VGS(OFF) must be lower than Vth. This relationship can be expressed as: VGS(OFF) < Vth < VGS(ON). Take this into consideration when using the device. Note 3: Pulse measurement. 5.2. Dynamic Characteristics (Unless otherwise specified, Ta = 25 �) Characteristics Input capacitance Reverse transfer capacitance Output capacitance Switching time (turn-on time) Switching time (turn-off time) Symbol Test Condition Ciss Crss Coss ton toff VDS = 10 V, VGS = 0 V, f = 1 MHz VDD = 10 V, ID = 2.0 A VGS = 0 to 2.5 V, RG = 4.7 Ω See Chapter 5.3. Min Typ. Max Unit � 200 � pF � 13 � � 40 � � 9 � ns � 9.5 � 5.3. Switching Time Test Circuit Fig. 5.3.1 Switching Time Test Circuit Fig. 5.3.2 Input Waveform/Output Waveform 5.4. Gate Charge Characteristics (Unless otherwise specified, Ta = 25 �) Characteristics Total gate charge (gate-source plus gate-drain) Gate-source charge 1 Gate-drain charge Symbol Test Condition Qg Qgs1 Qgd VDD = 10 V, VGS = 4.5 V, ID = 2.4 A Min Typ. Max Unit � 2.2 � nC � 0.5 � � 0.9 � ©2021 3 Toshiba Electronic Devices & Storage Corporation 2021-09-14 Rev.3.0 SSM3K324R 5.5. Source-Drain Characteristics (Unless otherwise specified, Ta = 25 �) Characteristics Diode forward voltage Note 1: Pulse measurement. 6. Marking Symbol Test Condition (Note 1) VDSF ID = -4.0 A, VGS = 0 V Min Typ. Max Unit � -0.8 -1.2 V Fig. 6.1 Marking ©2021 4 Toshiba Electronic Devices & Storage Corporation 2021-09-14 Rev.3.


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