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HCTS75MS Dataheets PDF



Part Number HCTS75MS
Manufacturers Intersil Corporation
Logo Intersil Corporation
Description Radiation Hardened Dual 2-Bit Bistable Transparent Latch
Datasheet HCTS75MS DatasheetHCTS75MS Datasheet (PDF)

HCTS75MS September 1995 Radiation Hardened Dual 2-Bit Bistable Transparent Latch Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW Q0 1 D0 1 D1 1 E 2 VCC D0 2 D1 2 Q1 2 1 2 3 4 5 6 7 8 16 1 Q0 15 1 Q1 14 1 Q1 13 1 E 12 11 GND 2 Q0 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Surv.

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HCTS75MS September 1995 Radiation Hardened Dual 2-Bit Bistable Transparent Latch Pinouts 16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T16, LEAD FINISH C TOP VIEW Q0 1 D0 1 D1 1 E 2 VCC D0 2 D1 2 Q1 2 1 2 3 4 5 6 7 8 16 1 Q0 15 1 Q1 14 1 Q1 13 1 E 12 11 GND 2 Q0 Features • 3 Micron Radiation Hardened SOS CMOS • Total Dose 200K RAD (Si) • SEP Effective LET No Upsets: >100 MEV-cm2/mg • Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) • Dose Rate Survivability: >1 x 1012 RAD (Si)/s • Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse • Latch-Up Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • LSTTL Input Compatibility - VIL = 0.8V Max - VIH = VCC/2 Min • Input Current Levels Ii ≤ 5µA at VOL, VOH 10 2 Q0 9 2 Q1 16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C TOP VIEW Q0 1 D0 1 D1 1 E 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 Q0 1 Q1 1 Q1 1 E GND 2 Q0 2 Q0 2 Q1 Description The Intersil HCTS75MS is a Radiation Hardened dual 2-bit bistable transparent latch. Each of the two latches are controlled by a separate enable input (E) which are active low. E low latches the output state. The HCTS75MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCTS75MS is supplied in a 16 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). VCC D0 2 D1 2 Q1 2 Functional Diagram 2(6) D0 13(4) E LATCH 0 16(10 D LE Q LE 1(11 Ordering Information 14(8 PART NUMBER HCTS75DMSR TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC +25oC +25oC +25oC SCREENING LEVEL Intersil Class S Equivalent Intersil Class S Equivalent Sample PACKAGE 16 Lead SBDIP 3(7) D1 5 12 VCC GND LE D LE 15(9 Q LATCH 1 HCTS75KMSR 16 Lead Ceramic Flatpack 16 Lead SBDIP TRUTH TABLE INPUTS D E H H L Q L H Q0 OUTPUTS Q H L Q0 HCTS75D/ Sample HCTS75K/ Sample HCTS75HMSR Sample 16 Lead Ceramic Flatpack Die L H Die X CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 Spec Number File Number 470 518625 3189.1 Specifications HCTS75MS Absolute Maximum Ratings Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA DC Drain Current, Any One Output . . . . . . . . . . . . . . . . . . . . . . .±25mA (All Voltage Reference to the VSS Terminal) Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265oC Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Reliability Information Thermal Resistance θJA θJC SBDIP Package. . . . . . . . . . . . . . . . . . . . 73oC/W 24oC/W Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/oC Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/oC CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation. Operating Conditions Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . 100ns/V Max Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . .VCC/2 to VCC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2, 3 Output Current (Sink) IOL VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0V 1 2, 3 Output Current (Source) IOH VCC = VIH = 4.5V, VOUT = VCC - 0.4V, VIL = 0V VCC = 5.5V, VIH = 2.75V, VIL = 0.8V, IOL = 50µA VCC = 4.5V, VIH = 2.25V, VIL = 0.8V, IOL = 50µA Output Voltage High VOH VCC = 5.5V, VIH = 2.75V, VIL = 0..


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