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A3265DX Dataheets PDF



Part Number A3265DX
Manufacturers Actel
Logo Actel
Description Integrator FPGAs
Datasheet A3265DX DatasheetA3265DX Datasheet (PDF)

Discontinued – v3.0 v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families F ea t u re s H ig h C a p ac it y G e n e ra l D es c ri p t i o n • • • • • • • • 2,500 to 30,000 Logic Gates Up to 3Kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 250 User-Programmable I/O Pins 225 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode H ig h P e r f o r m a nc e Actel’s Integrator Series FPGAs are the first programmable logic devices optimized.

  A3265DX   A3265DX



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Discontinued – v3.0 v3.0 Integrator Series FPGAs: 1200XL and 3200DX Families F ea t u re s H ig h C a p ac it y G e n e ra l D es c ri p t i o n • • • • • • • • 2,500 to 30,000 Logic Gates Up to 3Kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry Up to 250 User-Programmable I/O Pins 225 MHz Performance 5 ns Dual-Port SRAM Access 100 MHz FIFOs 7.5 ns 35-Bit Address Decode H ig h P e r f o r m a nc e Actel’s Integrator Series FPGAs are the first programmable logic devices optimized for high-speed system logic integration. Based on Actel’s proprietary antifuse technology and 0.6-micron double metal CMOS process, Integrator Series devices offer a fine-grained, register-rich architecture with embedded dual-port SRAM and wide-decode circuitry. Integrator Series’ 3200DX and 1200XL families were designed to integrate system logic which is typically implemented in multiple CPLDs, PALs, and FPGAs. These devices provide the features and performance required for today’s complex, high-speed digital logic systems. The 3200DX family offers fast dual-port SRAM for implementing FIFOs, LIFOs, and temporary data storage. The large number of storage elements can efficiently address applications requiring wide datapath manipulation and transformation functions such as telecommunications, networking, and DSP. E a s e - of -I n t e g r a t i o n • Synthesis-Friendly Architecture Supports ASIC Design Methodologies. • 95–100% Device Utilization using Automatic Place-and-Route Tools. • Deterministic, User-Controllable Timing Via Timing Driven Software Tools with Up To 100% Pin Fixing. • IEEE Standard 1149.1 (JTAG) Boundary Scan Testing. In t eg r a to r S e ri e s P ro d u ct P r of i l e F a m i l y 1200XL Device A1225XL 2,500 N/A 231 220 N/A N/A 231 2 83 No A1240XL 4,000 N/A 348 336 N/A N/A 348 2 104 No A1280XL 8,000 N/A 624 608 N/A N/A 624 2 140 No 3200DX A3265DX 6,500 N/A 510 475 20 N/A 510 2 126 No PL84 PQ100 PQ160 TQ176 A32100DX 10,000 2,048 700 662 20 8 700 6 152 Yes PL84 PQ160 PQ208 TQ176 CQ84 A32140DX 14,000 N/A 954 912 24 N/A 954 2 176 Yes PL84 PQ160 PQ208 TQ176 CQ256 A32200DX 20,000 2,560 1,230 1,184 24 10 1,230 6 202 Yes PQ208 RQ208 RQ240 CQ208 CQ256 A32300DX 30,000 3,072 1,888 1,833 28 12 1,888 6 250 Yes RQ208 RQ240 CQ256 Capacity Logic Gates1 SRAM Bits Sequential Combinatorial Decode Logic Modules SRAM Modules (64x4 or 32x8) Dedicated Flip-Flops Clocks User I/O (Maximum) JTAG Packages PL84 PQ100 VQ100 PG100 PL84 PQ100 PQ144 TQ176 PG132 PL84 PQ160 PQ208 TQ176 PG176 CQ172 Note: Logic gate capacity does not include SRAM bits as logic. February 2001 1 © 2001 Actel Corporation I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s O r d er i n g In f or m a t i o n A1225 XL V – PQ 100 C Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Package Type CQ = Ceramic Quad Flat Pack PG = Ceramic.


A1280XL A3265DX A32100DX


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