Differential Clock Buffer/Driver
CY28351
Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
Features
• Supports 333-MHz and 400-MHz DDR SDRAM...
Description
CY28351
Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
Features
Supports 333-MHz and 400-MHz DDR SDRAM 60- – 200-MHz operating frequency Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications Distributes one clock input to ten differential outputs External feedback pin (FBIN) is used to synchronize the outputs to the clock input Conforms to the DDRI specification Spread Aware for electromagnetic interference (EMI) reduction 48-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for the test purposes. The PLL in this device uses the input clock (CLKIN) and the feedback clock (FBIN) to provide high-performance, low-skew, low-jitter output differential clocks.
Block Diagram
10
Pin Configuration
YT0 YC0 YT1 YC1 YT2 YC2
SCLK SDATA
YT4 YC4 YT5 YC5 YT6 YC6
CLKIN PLL FBIN
YT7 YC7 YT8 YC8 YT9 YC9
CY28351
Serial Interface Logic
YT3 YC3
AVDD FBOUT
VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKIN NC VDDI AVDD AVSS VSS YC...
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