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74S112

Fairchild Semiconductor

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop


Description
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with comp...



Fairchild Semiconductor

74S112

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