Radiation Hardened Octal Transparent Latch
HCS573MS
September 1995
Radiation Hardened Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE ME...
Description
HCS573MS
September 1995
Radiation Hardened Octal Transparent Latch, Three-State
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T20, LEAD FINISH C TOP VIEW
OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 20 VCC 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7 11 LE
Features
3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/BitDay (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Fanout (Over Temperature Range) - Bus Driver Outputs - 15 LSTTL Loads Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels - VIL = 0.3 VCC Max - VIH = 0.7 VCC Min Input Current Levels Ii ≤ 5µA at VOL, VOH
GND 10
Description
The Intersil HCS573MS is a Radiation Hardened octal transparent three-state latch with an active low output enable. The HCS573MS utilizes advanced CMOS/SOS technology. The outputs are transparent to the inputs when the Latch Enable (LE) is HIGH. When the Latch Enable (LE) goes LOW, the data is latched. The Output Enable (OE) controls the tri-state outputs. When the Output Enable (OE) is HIGH, the outputs are in the high impedance state. The latch operation is independent of the state of the Output Enable. The HCS573MS utilizes advanced ...
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