HCS125MS

HCS125MS September 1995 Radiation Hardened Quad Buffer, Three-State Pinouts 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T14, LEAD FINISH C TOP VIEW OE1 1 A1 2 Y1 3 OE2 4 A2 5 Y2 6 GND 7 14 VCC 13 OE4 12 A4 11 Y4 10 OE3 9 A3 8 Y3 Features 3 Micron Radiation Hardened SOS CMOS Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >1010 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels - VIL = 30% of VCC Max - VIH = 70% of VCC Min Input Current Levels Ii ≤ 5µA at VOL, VOH Description The Intersil HCS125MS is a Radiation Hardened quad three-state buffer, each having its own output enable input. A high level on the enable input puts the output in a high impedance state. The HCS125MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS125MS is supplied in a 14 lead Ceramic flatpack (K suffix) or a SBDIP Package (D suffix). OE1 A1 Y1 OE2 A2 Y2 GND 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F14, LEAD FINISH C TOP VIEW 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 A4 Y4 OE3 A3 Y3 Ordering Informati...