FPGA fabric
LatticeXP2™ Family Data Sheet
DS1009 Version 2.2, September 2014
LatticeXP2 Family Data Sheet Introduction
February 20...
Description
LatticeXP2™ Family Data Sheet
DS1009 Version 2.2, September 2014
LatticeXP2 Family Data Sheet Introduction
February 2012
Features
flexiFLASH™ Architecture
Instant-on Infinitely reconfigurable Single chip FlashBAK™ technology Serial TAG memory Design security
Live Update Technology
TransFR™ technology Secure updates with 128 bit AES encryption Dual-boot with external SPI
sysDSP™ Block
Three to eight blocks for high performance Multiply and Accumulate
12 to 32 18x18 multipliers Each block supports one 36x36 multiplier or four
18x18 or eight 9x9 multipliers
Embedded and Distributed Memory
Up to 885 Kbits sysMEM™ EBR Up to 83 Kbits Distributed RAM
sysCLOCK™ PLLs
Up to four analog PLLs per device Clock multiply, divide and phase shifting
Data Sheet DS1009
Flexible I/O Buffer
sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II – HSTL15 class I; HSTL18 class I, II – PCI – LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS
Pre-engineered Source Synchronous Interfaces
DDR / DDR2 interfaces up to 200 MHz 7:1 LVDS interfaces support display applications XGMII
Density And Package Options
5k to 40k LUT4s, 86 to 540 I/Os csBGA, TQFP, PQFP, ftBGA and fpBGA packages Density migration supported
Flexible Device Configuration
SPI (master and slave) Boot Flash Interface Dual Boot Image supported Soft Error Detect (SED) macro embedded
System Level Support
IEEE 1149.1 and IEEE 1532 Compliant On-chip os...
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