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PHK18NQ03LT Dataheets PDF



Part Number PHK18NQ03LT
Manufacturers NXP
Logo NXP
Description N-channel TrenchMOS logic level FET
Datasheet PHK18NQ03LT DatasheetPHK18NQ03LT Datasheet (PDF)

SO 8 PHK18NQ03LT N-channel TrenchMOS logic level FET Rev. 03 — 17 March 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits „ High efficiency due to low switching and conduction losses „ Suitable for logic level gate d.

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SO 8 PHK18NQ03LT N-channel TrenchMOS logic level FET Rev. 03 — 17 March 2011 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits „ High efficiency due to low switching and conduction losses „ Suitable for logic level gate drive sources 1.3 Applications „ DC-to-DC converters „ Notebook computers „ Switched-mode power supplies „ Voltage regulators 1.4 Quick reference data Table 1. Symbol VDS ID Ptot RDSon Quick reference data Parameter drain-source voltage drain current total power dissipation drain-source on-state resistance Conditions Tj ≥ 25 °C; Tj ≤ 150 °C Tsp = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 Tsp = 25 °C; see Figure 2 VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 VGS = 4.5 V; ID = 15 A; VDS = 12 V; see Figure 12; see Figure 13 Min Typ 7.1 Max Unit 30 V 20.3 A 6.25 W 8.9 mΩ Static characteristics Dynamic characteristics QGD gate-drain charge 2.5 nC NXP Semiconductors PHK18NQ03LT N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 Pinning information Symbol Description S S S G D D D D source source source gate drain drain drain drain 1 4 mbb076 Simplified outline 8 5 Graphic symbol D G S SOT96-1 (SO8) 3. Ordering information Table 3. Ordering information Package Name PHK18NQ03LT SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number 4. Limiting values Table 4. Symbol VDS VDGR VGS ID Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current Tsp = 25 °C; VGS = 10 V; see Figure 1; see Figure 3 Tsp = 100 °C; VGS = 10 V; see Figure 1 IDM Ptot Tstg Tj IS ISM EDS(AL)S peak drain current total power dissipation storage temperature junction temperature source current peak source current non-repetitive drain-source avalanche energy Tsp = 25 °C Tsp = 25 °C; pulsed; tp ≤ 10 µs VGS = 10 V; Tj(init) = 25 °C; ID = 31.5 A; Vsup ≤ 25 V; unclamped; tp = 0.07 ms; RGS = 50 Ω Tsp = 25 °C; pulsed; tp ≤ 10 µs; see Figure 3 Tsp = 25 °C; see Figure 2 Conditions Tj ≥ 25 °C; Tj ≤ 150 °C Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ Min -20 -55 -55 Max 30 30 20 20.3 12.1 80 6.25 150 150 5.2 20.8 50 Unit V V V A A A W °C °C A A mJ In accordance with the Absolute Maximum Rating System (IEC 60134). Source-drain diode Avalanche ruggedness PHK18NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 03 — 17 March 2011 2 of 13 NXP Semiconductors PHK18NQ03LT N-channel TrenchMOS logic level FET 120 Ider (%) 80 03aa25 120 Pder (%) 80 03aa17 40 40 0 0 50 100 150 Tsp (°C) 200 0 0 50 100 150 Tsp (°C) 200 Fig 1. Normalized continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of solder point temperature 003aaa680 103 ID (A) 102 tp = 10 μ s 10 100 μ s 1 ms DC 10 ms 1 100 ms Limit RDSon = VDS / ID 10-1 10-1 1 10 VDS (V) 102 Tsp = 25 °C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHK18NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 03 — 17 March 2011 3 of 13 NXP Semiconductors PHK18NQ03LT N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-sp) Thermal characteristics Parameter thermal resistance from junction to solder point Conditions Min Typ Max 20 Unit K/W 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 0.1 1 0.05 0.02 single pulse 10-1 10-5 tp T P 003aaa681 δ= tp T t 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration PHK18NQ03LT All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 03 — 17 March 2011 4 of 13 NXP Semiconductors PHK18NQ03LT N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage Conditions ID = 250 µA; VGS = 0 V; Tj = 25 °C ID = 250 µA; VGS = 0 V; Tj = -55 °C Min 30 27 1.3 0.8 ID = 15 A; VDS = 12 V; see Figure 12; see Figure 13 VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 VDS = 0 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 Coss Crss td(on) tr td(off) tf output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 VDS = 12 V; RL = 0.8 Ω; VGS = 4.5 V; RG(ext) = 5.6 Ω Typ 1.7 7.1 12.1 10.1 1.6 10.6 4.85 2.4 2.45 2.5 3 1380 159.


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