BUK9K52-60E

LF BUK9K52-60E 17 June 2013 PA K 56D Dual N-channel TrenchMOS logic level FET Product data sheet 1. General description Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits Q101 compliant Repetitive avalanche rated Suitable for thermally demanding environments due to 175 °C rating True logic level gate with VGS(th) > 0.5 V @ 175 °C 3. Applications 12 V Automotive systems Motors, lamps and solenoid control Start-stop micro-hybrid applications Transmission control Ultra high performance power switching 4. Quick reference data Table 1. Symbol VDS ID Ptot RDSon Quick reference data Parameter drain-source voltage drain current total power dissipation Conditions Tj ≥ 25 °C; Tj ≤ 175 °C VGS = 5 V; Tmb = 25 °C; Fig. 1 Tmb = 25 °C; Fig. 2 VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12 Min Typ Max 60 16 32 Unit V A W Static characteristics FET1 and FET2 drain-source on-state resistance gate-drain charge 47.3 55 mΩ Dynamic characteristics FET1 and FET2 QGD ID = 5 A; VDS = 48 V; VGS = 5 V; Tj = 25 °C; Fig. 14; Fig. 15 2.3 nC Scan or click this QR code to view the latest information for this product NXP Semiconductors BUK9K52-60E Dual N-channel TrenchMOS logic level FET 5. Pinning information Table 2. Pin 1 2 3 4 5 6 7 8 Pinning information Symbol Description S1 G1 S2 G2 D2 D2 D1 D1 source1...