Document
WPCT301/NPCT501 Trusted Platform Module (TPM) Version 1.2 with I2C Interface
March 2011 Revision 1.40
WPCT301/NPCT501 Trusted Platform Module (TPM) Version 1.2 with I2C Interface
General Description
The Nuvoton WPCT301/NPCT501 family of single-chip Trusted Platform Modules (TPM) is a third-generation Nuvoton SafeKeeper device that implements the TCG version 1.2 specification for PC-Client TPM with the addition of a serial data interface. The WPCT301/NPCT501 is designed to reduce system power-up time and Trusted OS loading time. It provides a complete platform security solution for a wide range of computer systems.
Bus Interface
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I2C Bus Interface — I2C Slave — Up to 400 KHz clock operation (NPCT501)
Clocking and Supply
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Features
General
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Complete, single-chip TPM solution — No external parts required Compatible with the Trusted Computing Group (TCG) TPM 1.2 Main Host Interface — TPM 1.2 Interface (TIS) emulation — Dedicated Interrupt signal Secure General-Purpose I/O (GPIO) — Up to three GPIO pins — I/O pins individually configured as input or output — Configurable internal pull-up resistors — TCG 1.2-defined interface — Dedicated Physical Presence (PP) pin with configurable pull-up or pull-down resistor Tick Counter
On-Chip Clock Generator Power Supply — 3.3V supply operation — Separate pins for main (VDD) and standby (VSB) power supplies — Low standby power consumption
Package
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28-pin Thin Shrink Small Outline Package (TSSOP28)
System Block Diagram
Host
I2C Bus Physical Presence
WPCT301/ NPCT501
GPIO
© 2011 Nuvoton Technology Corporation
www.nuvoton.com
WPCT301/NPCT501
Datasheet Revision Record
Revision Date February 2008 March 2008 April 2008 Status Revision 0.9 Revision 1.0 Preliminary Datasheet Preliminary Datasheet, second release Comments
Revision 1.01 Removed tWLB requirement Fixed SPI_DO I/O definition in 1.3.1 Serial Interface Fixed signal names in 3.4.3 I2C Timing and 3.4.4 SPI Timing diagrams In 3.4.4 SPI Timing diagram, changed Max frequency of tSCK (SPI Timing) to 100 KHz Revision 1.02 In 3.4.4 SPI Timing diagram, changed Max frequency of tSCK (SPI Timing) to 200 KHz Replaced Figures 11 and 12 (page 20) Revision 1.03 Nuvoton revision. Changed logos and company name. Revision 1.04 Order numbers changed (...0WG to ...0WX) Added description to SADD pin Revision 1.05 Changed power-well to VDD for all pins in Section 1 (Signal/Pin Connection and Description). Changed SADD description in Section 1.3.3. Changed Section 1.4 (Internal Pull-up and Pull-down Resistors). Changed Section 4.4.2 (Reset Timing). Updated Table 1 (“Buffer Types”) and updated Section 1.3 (“Signal/Pin Description”) tables, accordingly. Revision 1.10 Removed references to the Nuvoton WPCT300 (SPI Interface). Added the NPCT501 device. Revision 1.20 Typo fixes. Added TPM Host Interface description (Section 3). Revision 1.30 Changed tSRST max requirement from 2.5 s to none, in Power-Up Reset Timing table (Section 4.4.2). Added tRST.STA to I2C Timing table (Section 4.4.3).
June 2008
November 2009 January 2010 August 2010
December 2010 January 2011 March 2011
March 2011
Revision 1.40 Added NPCT501MA0WX order number to pinout diagram and back cover.
www.nuvoton.com
2
Revision 1.40
WPCT301/NPCT501
Table of Contents
1.0
Signal/Pin Connection and Description
1.1 1.2 1.3 CONNECTION DIAGRAM ........................................................................................................... 4 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 4 SIGNAL/PIN DESCRIPTIONS ..................................................................................................... 5 1.3.1 Serial Interface .............................................................................................................. 5 1.3.2 Inputs and Outputs ....................................................................................................... 5 1.3.3 Configuration Straps and Testing .................................................................................. 5 1.3.4 Power and Ground ........................................................................................................ 5 1.3.5 Reserved ....................................................................................................................... 6 INTERNAL PULL-UP AND PULL-DOWN RESISTORS .............................................................. 6
1.4 2.0
Trusted Platform Module (TPM) Overview
2.1 2.2 2.3 2.4 SYSTEM CONNECTIONS .......................................................................................................... 7 POWER MANAGEMENT (PM) .................................................................................................... 7 HOST INTERFACE ..................................................................................................................... 7 RESET ...............................................................