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AT25BCM512B Dataheets PDF



Part Number AT25BCM512B
Manufacturers Adesto
Logo Adesto
Description 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory
Datasheet AT25BCM512B DatasheetAT25BCM512B Datasheet (PDF)

Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 70 MHz Maximum Operating Frequency – Clock-to-Output (tV) of 6 ns Maximum • Flexible, Optimized Erase Architecture for Code + Data Storage Applications – Uniform 4-Kbyte Block Erase – Uniform 32-Kbyte Block Erase – Full Chip Erase Hardware Controlled Locking of Protected Sectors via WP Pin 128-Byte Programmable OTP Security Register Flexible Programming – Byte/Page Program (1 to 2.

  AT25BCM512B   AT25BCM512B


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Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 70 MHz Maximum Operating Frequency – Clock-to-Output (tV) of 6 ns Maximum • Flexible, Optimized Erase Architecture for Code + Data Storage Applications – Uniform 4-Kbyte Block Erase – Uniform 32-Kbyte Block Erase – Full Chip Erase Hardware Controlled Locking of Protected Sectors via WP Pin 128-Byte Programmable OTP Security Register Flexible Programming – Byte/Page Program (1 to 256 Bytes) Fast Program and Erase Times – 2.5 ms Typical Page Program (256 Bytes) Time – 100 ms Typical 4-Kbyte Block Erase Time – 500 ms Typical 32-Kbyte Block Erase Time Automatic Checking and Reporting of Erase/Program Failures JEDEC Standard Manufacturer and Device ID Read Methodology Low Power Dissipation – 6 mA Active Read Current (Typical at 20 MHz) – 5 µA Deep Power-Down Current (Typical) Endurance: 100,000 Program/Erase Cycles Data Retention: 20 Years Complies with Full Industrial Temperature Range Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-pad Ultra Thin DFN (2 x 3 x 0.6 mm) • • • • • • • 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory AT25BCM512B Preliminary • • • • 1. Description The AT25BCM512B is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25BCM512B, with its erase granularity as small as 4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The erase block sizes of the AT25BCM512B have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. Specifically designed for use in 3-volt systems, the AT25BCM512B supports read, program, and erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing. 3704BX–DFLASH–11/2012 2. Pin Descriptions and Pinouts Table 2-1. Symbol Pin Descriptions Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance state. When the device is deselected, data will not be accepted on the SI pin. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standby mode until the completion of the operation. SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of data to and from the device. Command, address, and input data present on the SI pin is always latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling edge of SCK. SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input including command and address sequences. Data on the SI pin is always latched in on the rising edge of SCK. Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted). SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on the falling edge of SCK. The SO pin will be in a high-impedance state whenever the device is deselected (CS is deasserted). WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to “Protection Commands and Features” on page 11 for more details on protection features and the WP pin. The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used. However, it is recommended that the WP pin also be externally connected to VCC whenever possible. HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state..


LD7577 AT25BCM512B AT25DF011


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