HCF4517B

HCC/HCF4517B DUAL 64-STAGE STATIC SHIFT REGISTER . . . . . . . . . CLOCK FREQUENCY 12MHz (TYP.) AT VDD = 10V SCHMITT TRIGGER CLOCK INPUTS ALLOW OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES THREE-STATE OUTPUTS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURREN OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N°. 13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES” EY (Plastic Package) F (Ceramic Package) C1 (Chip Carrier) ORDER CODES : HCC4517BF HCF4517BM1 HCF4517BC1 PIN CONNECTIONS DESCRIPTION The HCC4517B (extended temperature range) and HCF4517B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. The HCC/HCF4517B dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32nd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted at the 17th, 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low-to-high transition. The truth table indicates how the clock and write enable inputs control the operation of the HCC/HCF4517B. Inputs at the intermediate taps allow entry of 64 bits into the register with 16 clo...