ADSP-21160N

SUMMARY High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backward compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-instruction, multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4M bits on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG) SHARC Digital Signal Processor ADSP-21160M/ADSP-21160N FEATURES 100 MHz (10 ns) core instruction rate (ADSP-21160N) Single-cycle instruction execution, including SIMD opera- tions in both computational units Dual data address generators (DAGs) with modulo and bit- reverse addressing Zero-overhead looping and single-cycle loop setup, provid- ing efficient program sequencing IEEE 1149.1 JTAG standard Test Access Port and on-chip emulation 400-ball 27 mm × 27 mm PBGA package Available in lead-free (RoHS compliant) package 200 million fixed-point MACs sustained performance (ADSP-21160N) CORE PROCESSOR TIMER INSTRUCTION CACHE 32 x 48-BIT DAG1 DAG2 8 x 4 x 32 8 x 4 x 32 PROGRAM SEQUENCER PM ADDRESS BUS 32 DM ADDRESS BUS 32 BUS CONNECT (PX) PM DATA BUS 16/32/40/48/64 DM DATA BUS 32/40/64 DUAL-PORTED SRAM TWO INDEPEN...