SSTV16859

INTEGRATED CIRCUITS SSTV16859 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM Product data 2000 Dec 01 File under Integrated Circuits — ICL03 2002 Feb 19 Philips Semiconductors Philips Semiconductors Product data 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 FEATURES Stub-series terminated logic for 2.5 V VDD (SSTL_2) Optimized for stacked DDR (Double Data Rate) SDRAM applications DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going high, and CK going low. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The dev...