HD74HCT125

HD74HCT125/HD74HCT126 Quad. Bus Buffer Gates (with 3-state outputs) Description The HD74HCT125, HD74HCT126 require the 3-state control input C to be taken high to put the output into the high impedance condition, whereas the HD74HCT125, HD74HCT126 requires the control input to be low to put the output into high impedance. Features LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A to Y) = 12 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Input C HCT125 H L L HCT126 L H H A X L H Output Y HD74HCT125 Z L H HD74HCT126 Z L H Notes: X: Irrelevant Z: Off (High-impedance) state of a 3-state output. HD74HCT125/HD74HCT126 Pin Arrangement HD74HCT125 1C 1A 1Y 2C 2A 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4C 4A 4Y 3C 3A 3Y (Top view) HD74HCT126 1C 1A 1Y 2C 2A 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4C 4A 4Y 3C 3A 3Y (Top view) 2 HD74HCT125/HD74HCT126 Absolute Maximum Ratings Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT I OUT I CC, I GND I IK I OK PT Tstg Rating –0.5 to +7.0 –0.5 to VCC + 0.5 –0.5 to VCC + 0.5 ±35 ±75 ±20 ±20 500 –65 to +150 Unit V V V mA mA mA ...